Zynq YOLOv3-Tiny INT8 FPGA Accelerator

An HDL-focused source release of a single-class YOLOv3-Tiny accelerator for Xilinx Zynq-7000. The repository contains the Verilog accelerator, simulation sources, selected Vivado configuration, and reviewed bare-metal C control code. Python training, inference, and parameter-export code is intentionally not included.

• 54 Verilog source files and one separately licensed VHDL component.
• Eight-lane INT8 convolution datapath with packed multiplication and accumulation.
• Programmable requantization, lookup-table activation, max pooling, and upsampling.
• AXI4-Stream feature/parameter transport and AXI4-Lite control.
• Bare-metal Zynq code for DMA, layer scheduling, parameter loading, detection decoding, and bounding-box control.
• Selected Vivado/Vitis 2019.2 reconstruction inputs for xc7z100ffg900-2.
• English architecture notes and an editable translated network-description document.

flowchart LR
    camera["External OV5640 camera IP"] --> capture["Capture and resize"]
    capture --> memory["DDR through VDMA"]
    memory <--> ps["Zynq processing system<br/>bare-metal control"]
    ps <--> dma["AXI DMA"]
    dma <--> accel["INT8 YOLO accelerator"]
    ps --> box["Bounding-box registers"]
    memory --> overlay["Video and box overlay"]
    box --> overlay
    overlay --> hdmi["HDMI output"]

The processing system coordinates DMA transfers and layer execution. The programmable logic performs the INT8 convolution pipeline and contains the retained resize, overlay, and HDMI integration sources. The camera IP shown above is an architectural dependency: its original implementation was excluded because redistribution permission was not established.

For more detail, see Architecture and the editable English network description.

The exact included and excluded file classes are recorded in Source Release Manifest.

The two ZIP files are convenience copies for browser-based transfer. They do not define a different license: archived files retain the same per-file notices and exceptions described in Licensing.

• AMD/Xilinx Vivado 2019.2.
• AMD/Xilinx Vitis 2019.2.
• Target part: xc7z100ffg900-2.
• AXI DMA and VDMA-based data movement.
• An OV5640 camera and compatible HDMI hardware are required for the complete demonstration.

The original project did not record a Vivado board part. Verify the retained pin constraints, DDR configuration, camera wiring, and HDMI interface against the actual board before use.

The retained vivado_prj/ directory is a source-only subset. It does not include a machine-specific .xpr, generated IP output products, runs, reports, netlists, bitstreams, XSA files, BSPs, or debug output.

A conservative reconstruction flow is:

1. Create a Vivado 2019.2 project for xc7z100ffg900-2.
2. Add the Verilog under src/ and the reviewed HDL under ip_repo/.
3. source vivado_prj/design_1_bd.tcl and repair the missing camera-IP reference with a compatible redistributable implementation.
4. Add zynq7100.xdc only after checking every pin against the target board.
5. Import the retained .xci configurations and regenerate all vendor output products locally.
6. Run synthesis and implementation, review every warning, and export a new XSA.
7. Generate a Vitis platform/BSP locally and add the reviewed sources under Vitis/Yolo/src/.

No clean reconstruction from this subset has yet been demonstrated.

This repository does not include model-training code, checkpoints, datasets, external parameter binaries, or sample images. The firmware expects externally prepared binary weights, biases, and activation parameters on a FAT-formatted SD card; filenames and load addresses are defined in yolo_load_param.c and yolo_load_param.h. Some retained simulation and firmware sources contain embedded test or configuration values; their provenance boundary is documented in Licensing.

Only use parameter files that you are entitled to distribute. Validate every file size, tensor layout, zero point, multiplier, and shift against the RTL before running the accelerator. The current loader also needs stronger short-read and error handling.

The following values were extracted from generated reports in the original private workspace. The reports themselves are intentionally excluded, and these numbers are not evidence of a clean rebuild.

The archived routed whole design did not meet all timing constraints: WNS was -6.309 ns, TNS was -624.100 ns, and 101 setup endpoints failed. The accelerator 200 MHz intra-clock group reported +0.062 ns WNS; the recorded failure was on a crossing to the 74.25 MHz video clock.

• The restricted OV5640/SCCB implementations are absent, so the complete camera system cannot currently build.
• The parameter-generation and model-training pipeline is not included.
• The firmware is configured for a single-class demonstration and retains only one best candidate box.
• The decoder does not implement general multi-box thresholding or non-maximum suppression.
• One Layer 22 address expression and the historical detection-head bias lengths require review.
• quant_int8.v has no explicit signed saturation clamp; verify it against an independent golden integer reference.
• The retained simulations are not self-checking and have no committed golden PASS logs.
• Timing closure, numerical equivalence, accuracy, latency, frame rate, and end-to-end board operation have not been reproduced from this source subset.

Original project material owned by a2307588073-arch is licensed under the MIT License. This grant is limited to material for which the copyright holder has licensing authority; it does not relicense third-party, vendor-controlled, generated, or provenance-unresolved content.

TMDSEncoder.vhd retains its Digilent BSD-3-Clause notice. AMD/Xilinx configuration and template-derived material remains subject to applicable vendor terms. The excluded camera implementations must not be reintroduced without redistribution permission or a compatible replacement. See Licensing and Third-Party Notices.