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riscv_dis_shift_xlen_2
Tsukasa OI edited this page Oct 19, 2022
·
6 revisions
- Branch:
riscv-dis-shift-xlen-2
- Tracking PR: #25 (view Pull Request and Diff)
- Mailing List:
- PATCH v1 (2022-07-30)
In the disassembler, there's no validation whether shift amount is valid on specific architecture.
Idea 1 patchset fixes that by adding xlen
argument to match_func
(in opcode entries).
Idea 2 patchset (this patchset) fixes that by printing invalid0x[SHAMT]
instead of actual shift width (SHAMT
in hexadecimal). If we don't have to print "unrecognized instruction" (such as .4byte
) on instrucitons with invalid shift amounts, this patch would be the simplest solution for the invalid shift amount checking support on the disassembler.
This patchset supports styling.
Invalid shift amounts are printed as text
, not immediate
.