Fix coproc halt esp32s3#7115
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This has survived dozen of iterations of |
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This always trips me up, and starting a build without doing it can even leave the build in a messed up state. The outer 'if' enables ci_set_matrix's way of invoking the Makefile still work properly.
microdev1
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The Technical Reference Manual for both esp32s2/s3 mentions the following halt sequence.
Before setting ULP-RISC-V to HALT, users should configure the register RTC_CNTL_COCPU_DONE first,
therefore, it is recommended to end the flashed program with the following pattern:
– Set the register RTC_CNTL_COCPU_DONE to end the operation of ULP-RISC-V and put it into halt;
– Set the register RTC_CNTL_COCPU_SHUT_RESET_EN to reset ULP-RISC-V.
Enough time is reserved for the ULP-RISC-V to complete the operations above before it goes to halt.
I suspect the root cause of the problem is something else.
I'll test with esp32s2 to check if it has the same issue, I believe both s2/s3 share the same coproc design.
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Any update @microdev1? |
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@jepler Can you run the same code (both ulp and circuitpython) on esp32s2 as well. |
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closing since I no longer get exactly this problem; not sure why. |
I found that on the esp32-s3-eye,
coproc.halt()frequently caused the main CPU to crash or CircuitPython to otherwisebecome unresponsive. After experimentation, I arrived at this alternate reset/halt sequence.
I didn't do any testing on S2.
Closes: #7109