Skip to content

0.1.10

Choose a tag to compare

View all tags
@alexforencich alexforencich released this 29 Apr 03:35
· 159 commits to master since this release
v0.1.10
f9ad915

This release represents a significant internal overhaul of the PCIe simulation framework. This includes a lot of clean-up, reworking, bug fixes, support for extended capabilities, and initial implementations of the link layer, ACK/NAK protocol, and flow control.

Notable changes in this release:

TLPs:

  • Improve TLP typing
  • Fix TLP address packing
  • Add LN and PH fields to TLP and update tag field to 10 bits
  • Ensure TLP payload data is always accessed via get_data and set_data
  • Store TLP payload as bytes instead of DWORDs
  • Add additional methods for TLP size information
  • Change default TLP packer and unpacker to return bytes
  • Copy data when copying TLP
  • Add sequence number field to TLP
  • Add flow control credit release callback to TLP

Link layer:

  • Add DLLP object
  • Add initial implementation of ACK/NAK protocol
  • Add initial implementation of flow control

Capabilities:

  • Reorganize capabilities to avoid mixins
  • Implement extended capability support
  • Add PCIe and AER extended capabilities
  • Add enums for capability and extended capability IDs
  • Add extended data to MSI capability
  • Add additional fields to PCIe capability
  • Raise exceptions when requested MSI operations fail

Configuration space:

  • Clean up configuration space implementation
  • Implement IO space and memory space enable bits

Simulation models:

  • Rework device number handling so only bus number is captured
  • Add match_tlp and match_secondary_tlp
  • Reimplement TLP routing in switch
  • Serialize calls to port rx_handler to prevent reordering and re-entering handler
  • Add SimPort, convert Port to a generic base class
  • Remove port from HostBridge
  • Release flow control credits when TLPs are consumed

IP core models:

  • Fix UltraScale model handling of sequence number and discontinue signals
  • Refactor UltraScale source and sink code to remove drive_frame and to avoid using pop on transmit
  • Pass through EP bit in UltraScale models
  • Pass link speed and width settings to port in UltraScale models
  • Expose flow control state in UltraScale models
Assets 4
Loading