If/Else for combinational assignment generates always @* that doesn't initialize #1629
Description
I think I've found a problem in the verilog generation. I've created a playground example here.
When you use an m.If(...)/m.Else() for a combinational assignment, an always @* block is generated. Now if one of the signals in the (automatically generated) sensitivity list changes, the block will be reevaluated - but it won't be evaluated at the start of the simulation.
That is one of the pitfalls that was fixed with always_comb in SystemVerilog. But as it is, this can lead to differences between the Amaranth simulation and other simulators. Even doing a reset does not "fix" this, as the signals in the sensitivity list will just be reset to the value that they already have because they were initialized to it, thus not triggering the always @* block.
You can of course work around this issue by just using a Mux(...), which will generate an assign statement. When creating multiple assignments that depend on the same conditions, using one m.If(...)/m.Else() is much cleaner though.