Context
Reviewer on #721 suggested supporting hardware design languages so AMD's HDL codebases can be indexed with the same tool.
Goal
Add parsers for Verilog / SystemVerilog / VHDL to src/gaia/code_index/parsers.py. Extract module, entity, architecture, and always-block boundaries as semantic chunks.
Acceptance
- Tree-sitter grammars (or equivalent) wired in for
.v, .sv, .vhd, .vhdl.
- Unit tests in
tests/unit/test_code_index_parsers.py cover sample HDL files and assert chunk boundaries on module/entity/architecture.
gaia-code index on a repo containing HDL files indexes them without error and returns sensible results for a query like "clock divider".
References
src/gaia/code_index/parsers.py — existing language parserstests/unit/test_code_index_parsers.py — test patterns to follow
Deferred from #721.
Context
Reviewer on #721 suggested supporting hardware design languages so AMD's HDL codebases can be indexed with the same tool.
Goal
Add parsers for Verilog / SystemVerilog / VHDL to
src/gaia/code_index/parsers.py. Extract module, entity, architecture, and always-block boundaries as semantic chunks.Acceptance
.v,.sv,.vhd,.vhdl.tests/unit/test_code_index_parsers.pycover sample HDL files and assert chunk boundaries on module/entity/architecture.gaia-code indexon a repo containing HDL files indexes them without error and returns sensible results for a query like "clock divider".References
src/gaia/code_index/parsers.py— existing language parserstests/unit/test_code_index_parsers.py— test patterns to followDeferred from #721.