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Update line endings#1

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ryansavino merged 1 commit into
amd:mainfrom
UnmeshDeodhar:fix-line-endings
Aug 24, 2023
Merged

Update line endings#1
ryansavino merged 1 commit into
amd:mainfrom
UnmeshDeodhar:fix-line-endings

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Remove line endings '\r' so it can be run on Linux conveniently.

Remove line endings '\r' so it can be run on Linux conveniently.

Signed-off-by: Unmesh Deodhar <udeodhar@amd.com>
@ryansavino ryansavino merged commit c4785fb into amd:main Aug 24, 2023
LakshmiSaiHarika added a commit to LakshmiSaiHarika/sev-utils that referenced this pull request Jan 24, 2025
Added  MSR 0xC0010010 check to validate if guest SEV, SEV-ES and SNP are enabled by reading SEV, SEV-ES and SNP bits from MSR 0xC0010010 instruction set

Bit #0 corresponds to the SEV bit status
Bit amd#1 corresponds to SEV-ES bit status
Bit amd#2 corresponds to SNP bit status

Signed-off-by: Harika Nittala <lnittala@amd.com>
LakshmiSaiHarika added a commit to LakshmiSaiHarika/sev-utils that referenced this pull request Jan 24, 2025
Added  MSR 0xC0010010 check to validate if guest SEV, SEV-ES and SNP are enabled by reading SEV, SEV-ES and SNP bits from MSR 0xC0010010 instruction set

Bit #0 corresponds to the SEV bit status
Bit amd#1 corresponds to SEV-ES bit status
Bit amd#2 corresponds to SNP bit status

Signed-off-by: Harika Nittala <lnittala@amd.com>
LakshmiSaiHarika added a commit to LakshmiSaiHarika/sev-utils that referenced this pull request Jan 24, 2025
Added  MSR 0xC0010010 check to validate if guest SEV, SEV-ES and SNP are enabled by reading SEV, SEV-ES and SNP bits from MSR 0xC0010010 instruction set

Bit #0 corresponds to the SEV bit status
Bit amd#1 corresponds to SEV-ES bit status
Bit amd#2 corresponds to SNP bit status

Signed-off-by: Harika Nittala <lnittala@amd.com>
LakshmiSaiHarika added a commit to LakshmiSaiHarika/sev-utils that referenced this pull request Jan 28, 2025
Added  MSR 0xC0010010 check to validate if guest SEV, SEV-ES and SNP are enabled by reading SEV, SEV-ES and SNP bits from MSR 0xC0010010 instruction set

Bit #0 corresponds to the SEV bit status
Bit amd#1 corresponds to SEV-ES bit status
Bit amd#2 corresponds to SNP bit status

Signed-off-by: Harika Nittala <lnittala@amd.com>
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2 participants