analogdevicesinc · tfcollins · May 21, 2019 · May 14, 2019 · May 14, 2019 · May 14, 2019
diff --git a/+adi/+common/DebugAttribute.m b/+adi/+common/DebugAttribute.m
@@ -1,6 +1,6 @@
 classdef (Abstract) DebugAttribute < matlabshared.libiio.base 
 
-    methods (Hidden, Access = protected)
+    methods (Hidden)
         function setDebugAttributeLongLong(obj,attr,value)
             phydev = getDev(obj, obj.phyDevName);
             if (nargin == 1)
@@ -26,13 +26,13 @@ function setDebugAttributeBool(obj,attr,value)
             end
             status = iio_device_debug_attr_write_bool(obj,phydev,attr,value);
             cstatus(obj,status,['Attribute write failed for : ' attr]);
-            % Check
-            [status, rValue] = iio_device_debug_attr_read_bool(obj,phydev,attr);
-            cstatus(obj,status,['Error reading attribute: ' attr]);
-            if value ~= rValue
-                status = -1;
-                cstatus(obj,status,['Attribute ' attr ' return value ' num2str(rValue) ', expected ' num2str(value)]);
-            end            
+            % Check (Not implemented yet)
+%             [status, rValue] = iio_device_debug_attr_read_bool(obj,phydev,attr);
+%             cstatus(obj,status,['Error reading attribute: ' attr]);
+%             if value ~= rValue
+%                 status = -1;
+%                 cstatus(obj,status,['Attribute ' attr ' return value ' num2str(rValue) ', expected ' num2str(value)]);
+%             end            
         end                
     end       
 end
diff --git a/+adi/+common/Rx.m b/+adi/+common/Rx.m
@@ -7,15 +7,20 @@
 
         function varargout = stepImpl(obj)
             % Get the data
-            [dataRAW, valid] = getData(obj);
-            index = 1;
             c = obj.channelCount/2;
-            varargout = cell(c+1,1);
-            for k = 1:c
-                varargout{k} = complex(dataRAW(index,:),dataRAW(index+1,:)).';
-                index = index+2;
+            if c > 0
+                [dataRAW, valid] = getData(obj);
+                index = 1;
+                varargout = cell(c+1,1);
+                for k = 1:c
+                    varargout{k} = complex(dataRAW(index,:),dataRAW(index+1,:)).';
+                    index = index+2;
+                end
+                varargout{end} = valid;
+            else
+                varargout = cell(1,1);
+                varargout{1} = true;
             end
-            varargout{end} = valid;
         end
 
     end

diff --git a/+adi/+common/RxTx.m b/+adi/+common/RxTx.m
@@ -106,14 +106,18 @@ function releaseChanBuffers(obj)
             obj.enabledChannels = true;
 
             % Create the buffers
-            status = createBuf(obj);
-            if status
-                for k=1:obj.channelCount
-                    disableChannel(obj, obj.channel_names{k}, obj.isOutput);
+            if obj.channelCount>0
+                status = createBuf(obj);
+                if status
+                    for k=1:obj.channelCount
+                        disableChannel(obj, obj.channel_names{k}, obj.isOutput);
+                    end
+                    releaseChanBuffers(obj);
+                    cerrmsg(obj,status,['Failed to create buffer for: ' obj.devName]);
+                    return
                 end
-                releaseChanBuffers(obj);
-                cerrmsg(obj,status,['Failed to create buffer for: ' obj.devName]);
-                return
+            else
+                status = 0;
             end
 
         end

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -30,7 +30,7 @@ build:master:
      - matlab
     stage: build
     script:
-     - export HDLBRANCH=master
+     - export HDLBRANCH=hdl_2018_r2
      - export MLRELEASE=R2018b
      - ./CI/scripts/dockermake build
      - export HDLBRANCH=
@@ -82,17 +82,35 @@ test_installer:2018_R1_Installer:
         reports:
             junit: test/BSPTestResults.xml
 
-# Test weekly fully sythesized design
-test:Synthesize:
-    when: manual
+# Test HWA no install
+test:2018_R1:
+    tags:
+     - vivado
+     - matlab
+    stage: test
+    dependencies:
+     - build:2018_R1
+    script:
+     - ./CI/scripts/dockermake test
+     - ./CI/scripts/dockermake zip
+    artifacts:
+        when: always
+        paths:
+            - zip/
+            - test/logs/
+        reports:
+            junit: test/BSPTestResults.xml
+
+# Test targeting demos (no hardware)
+test:targeting_demos:
     tags:
      - matlab
      - vivado
     stage: test
     dependencies:
      - build:2018_R1
     script:
-     - ./CI/scripts/dockermake test_synth
+     - ./CI/scripts/dockermake test_targeting_demos
     artifacts:
         when: always
         name: "$CI_COMMIT_REF_NAME"

diff --git a/CI/projects/adrv9361z7035/common/config_rx.tcl b/CI/projects/adrv9361z7035/common/config_rx.tcl
@@ -13,3 +13,14 @@ disconnect_bd_net /util_ad9361_adc_fifo_dout_data_3 [get_bd_pins util_ad9361_adc
 connect_bd_net [get_bd_pins util_ad9361_adc_pack/adc_valid_0] [get_bd_pins util_ad9361_adc_pack/adc_valid_1]
 connect_bd_net [get_bd_pins util_ad9361_adc_pack/adc_valid_0] [get_bd_pins util_ad9361_adc_pack/adc_valid_2]
 connect_bd_net [get_bd_pins util_ad9361_adc_pack/adc_valid_0] [get_bd_pins util_ad9361_adc_pack/adc_valid_3]
+
+global dma_config
+# Configure DMA
+if {[info exists dma_config]} {
+    if {$dma_config eq "Packetized"} {
+        set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64} CONFIG.DMA_DATA_WIDTH_DEST {256} CONFIG.SYNC_TRANSFER_START {false} CONFIG.DMA_AXI_PROTOCOL_DEST {0} CONFIG.DMA_TYPE_SRC {1} CONFIG.MAX_BYTES_PER_BURST {32768}] [get_bd_cells axi_ad9361_adc_dma]
+        connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_aclk] [get_bd_pins util_ad9361_divclk/clk_out]
+        connect_bd_net [get_bd_pins util_ad9361_adc_pack/adc_data] [get_bd_pins axi_ad9361_adc_dma/s_axis_data]
+        connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_valid] [get_bd_pins util_ad9361_adc_pack/adc_valid]
+    }
+}
diff --git a/CI/scripts/Docker b/CI/scripts/Docker
@@ -1,8 +1,10 @@
 FROM ubuntu:16.04
 
 MAINTAINER Travis Collins <travis.collins@analog.com>
-RUN apt update
+RUN DEBIAN_FRONTEND=noninteractive apt update
 RUN DEBIAN_FRONTEND=noninteractive apt-get install -y libpng-dev libfreetype6-dev libblas-dev liblapack-dev gfortran build-essential xorg
 RUN DEBIAN_FRONTEND=noninteractive apt-get install -y openjdk-8-jre openjdk-8-jdk libgtk2.0-0 libxss1 libxt6 zip unzip curl wget tar git xvfb
+RUN DEBIAN_FRONTEND=noninteractive apt-get install -y fakeroot libncurses5-dev libssl-dev ccache dfu-util u-boot-tools device-tree-compiler
+RUN DEBIAN_FRONTEND=noninteractive apt-get install -y libssl-dev mtools bc python cpio zip unzip rsync file wget
 RUN DEBIAN_FRONTEND=noninteractive dpkg --add-architecture i386
 RUN DEBIAN_FRONTEND=noninteractive apt-get install -y lib32stdc++6
diff --git a/CI/scripts/Makefile b/CI/scripts/Makefile
@@ -97,6 +97,9 @@ test_modem:
 test_synth:
 	bash synth_designs.sh
 
+test_targeting_demos:
+	bash targeting_designs.sh
+
 gen_tlbx:
 	${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "genTlbx;exit();"
 

diff --git a/CI/scripts/targeting_designs.sh b/CI/scripts/targeting_designs.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+
+MLFLAGS="-nodisplay -nodesktop -nosplash"
+
+if [ -z "$MLRELEASE" ]
+then
+	MLRELEASE=R2018b
+fi
+
+MLPATH=/usr/local/MATLAB
+
+cd ../.. 
+source /opt/Xilinx/Vivado/2017.4/settings64.sh
+Xvfb :77 &
+export DISPLAY=:77
+export SWT_GTK3=0
+source /opt/Xilinx/Vivado/2017.4/settings64.sh
+$MLPATH/$MLRELEASE/bin/matlab $MLFLAGS -r "addpath(genpath('test'));addpath(genpath('deps'));runDemoTests;"
+kill -9 `pidof Xvfb`
diff --git a/.../frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/add_rx_tx_io.m b/.../frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/add_rx_tx_io.m
@@ -0,0 +1,201 @@
+function add_rx_tx_io(hRD)
+
+% add AXI4 and AXI4-Lite slave interfaces
+hRD.addAXI4SlaveInterface( ...
+    'InterfaceConnection', 'axi_cpu_interconnect/M11_AXI', ...
+    'BaseAddress',         '0x43C00000', ...
+    'MasterAddressSpace',  'sys_ps7/Data');
+
+% % AGC control input for transceiver
+% hRD.addInternalIOInterface( ...
+%     'InterfaceID',    'Enable AGC', ...
+%     'InterfaceType',  'OUT', ...
+%     'PortName',       'en_agc', ...
+%     'PortWidth',      1, ...
+%     'InterfaceConnection', 'gpio_en_agc', ...
+%     'IsRequired',     false);
+
+% GPIO status output for transceiver
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'CTRL_STATUS', ...
+    'InterfaceType',  'IN', ...
+    'PortName',       'gpio_status', ...
+    'PortWidth',      8, ...
+    'InterfaceConnection', 'gpio_status', ...
+    'IsRequired',     false);
+
+% GPIO Control input for transceiver
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'AD9361 CTRL IN', ...
+    'InterfaceType',  'OUT', ...
+    'PortName',       'gpio_ctl', ...
+    'PortWidth',      4, ...
+    'InterfaceConnection', 'gpio_ctl', ...
+    'IsRequired',     false);
+
+% DMA Ready signal
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'DMA Ready', ...
+    'InterfaceType',  'IN', ...
+    'PortName',       'dma_rdy', ...
+    'PortWidth',      1, ...
+    'InterfaceConnection', 'axi_ad9361_adc_dma/s_axis_ready', ...
+    'IsRequired',     false);
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% Rx Reference design interfaces
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%	
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'IP Data Valid OUT', ...
+    'InterfaceType',  'OUT', ...
+    'PortName',       'dut_data_valid', ...
+    'PortWidth',      1, ...
+    'InterfaceConnection', 'util_ad9361_adc_pack/adc_valid_0', ...
+    'IsRequired',     false);
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'IP Data 0 OUT', ...
+    'InterfaceType',  'OUT', ...
+    'PortName',       'dut_data_0', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_0', ...
+    'IsRequired',     false);	
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'IP Data 1 OUT', ...
+    'InterfaceType',  'OUT', ...
+    'PortName',       'dut_data_1', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_1', ...
+    'IsRequired',     false);	
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'IP Data 2 OUT', ...
+    'InterfaceType',  'OUT', ...
+    'PortName',       'dut_data_2', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_2', ...
+    'IsRequired',     false);
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'IP Data 3 OUT', ...
+    'InterfaceType',  'OUT', ...
+    'PortName',       'dut_data_3', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_3', ...
+    'IsRequired',     false);		
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'AD9361 ADC Data I0', ...
+    'InterfaceType',  'IN', ...
+    'PortName',       'sys_wfifo_0_dma_wdata', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_0', ...
+    'IsRequired',     false);	
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'AD9361 ADC Data Q0', ...
+    'InterfaceType',  'IN', ...
+    'PortName',       'sys_wfifo_1_dma_wdata', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_1', ...
+    'IsRequired',     false);
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'AD9361 ADC Data I1', ...
+    'InterfaceType',  'IN', ...
+    'PortName',       'sys_wfifo_2_dma_wdata', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_2', ...
+    'IsRequired',     false);	
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'AD9361 ADC Data Q1', ...
+    'InterfaceType',  'IN', ...
+    'PortName',       'sys_wfifo_3_dma_wdata', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_3', ...
+    'IsRequired',     false);
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%	
+% Tx Reference design interfaces
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%	
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'AD9361 DAC Data I0', ...
+    'InterfaceType',  'OUT', ...
+    'PortName',       'axi_ad9361_dac_data_i0', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_0', ...
+    'IsRequired',     false);
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'AD9361 DAC Data Q0', ...
+    'InterfaceType',  'OUT', ...
+    'PortName',       'axi_ad9361_dac_data_q0', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_1', ...
+    'IsRequired',     false);	
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'AD9361 DAC Data I1', ...
+    'InterfaceType',  'OUT', ...
+    'PortName',       'axi_ad9361_dac_data_i1', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_2', ...
+    'IsRequired',     false);
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'AD9361 DAC Data Q1', ...
+    'InterfaceType',  'OUT', ...
+    'PortName',       'axi_ad9361_dac_data_q1', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_3', ...
+    'IsRequired',     false);	
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'IP Data 0 IN', ...
+    'InterfaceType',  'IN', ...
+    'PortName',       'util_dac_unpack_dac_data_00', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_0', ...
+    'IsRequired',     false);
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'IP Data 1 IN', ...
+    'InterfaceType',  'IN', ...
+    'PortName',       'util_dac_unpack_dac_data_01', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_1', ...
+    'IsRequired',     false);
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'IP Data 2 IN', ...
+    'InterfaceType',  'IN', ...
+    'PortName',       'util_dac_unpack_dac_data_02', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_2', ...
+    'IsRequired',     false);
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'IP Data 3 IN', ...
+    'InterfaceType',  'IN', ...
+    'PortName',       'util_dac_unpack_dac_data_03', ...
+    'PortWidth',      16, ...
+    'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_3', ...
+    'IsRequired',     false);	
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'IP Load Tx Data OUT', ...
+    'InterfaceType',  'OUT', ...
+    'PortName',       'util_dac_unpack_dac_valid_00', ...
+    'PortWidth',      1, ...
+    'InterfaceConnection', 'util_ad9361_dac_upack/dac_valid_0', ...
+    'IsRequired',     false);	
+
+hRD.addInternalIOInterface( ...
+    'InterfaceID',    'IP Valid Tx Data IN', ...
+    'InterfaceType',  'IN', ...
+    'PortName',       'util_dac_unpack_upack_valid_00', ...
+    'PortWidth',      1, ...
+    'InterfaceConnection', 'util_ad9361_dac_upack/upack_valid_0', ...
+    'IsRequired',     false);