Upgrade to R2019a and HDL 2018 R2

+adi/+common/DDS.m

@@ -51,7 +51,7 @@
     methods (Hidden, Access=protected)
 
         function ToggleDDS(obj,value)
-            chanPtr = getChan(obj,'altvoltage0',true);
+            chanPtr = getChan(obj,obj.iioDev,'altvoltage0',true);
             iio_channel_attr_write_bool(obj,chanPtr,'raw',value);
         end
 
@@ -60,7 +60,7 @@ function DDSUpdate(obj)
             for g=1:obj.channelCount/2
                 for k=1:4
                     id = sprintf('altvoltage%d',k-1);
-                    chanPtr = getChan(obj,id,true);
+                    chanPtr = getChan(obj,obj.iioDev,id,true);
                     iio_channel_attr_write_double(obj,chanPtr,'frequency',obj.DDSFrequencies(g,k));
                     iio_channel_attr_write_double(obj,chanPtr,'scale',obj.DDSScales(g,k));
                     iio_channel_attr_write_double(obj,chanPtr,'phase',obj.DDSPhases(g,k));

+adi/+common/RxTx.m

@@ -84,7 +84,7 @@ function releaseChanBuffers(obj)
             % Disable the channels
             if obj.enabledChannels
                 for k=1:obj.channelCount
-                    disableChannel(obj, obj.channel_names{k}, obj.isOutput);
+                    disableChannel(obj, obj.iioDev, obj.channel_names{k}, obj.isOutput);
                 end
                 obj.enabledChannels = false;
             end
@@ -101,7 +101,7 @@ function releaseChanBuffers(obj)
 
             % Enable the channel(s)
             for k=1:obj.channelCount
-                enableChannel(obj, obj.channel_names{k}, obj.isOutput);
+                enableChannel(obj, obj.iioDev, obj.channel_names{k}, obj.isOutput);
             end
             obj.enabledChannels = true;
 

.gitlab-ci.yml

@@ -5,12 +5,13 @@ stages:
   - deploy
 
 # Default build
-build:2018_R1:
+build:2018_R2:
     tags:
      - vivado
      - matlab
     stage: build
     script:
+     - export MLRELEASE=R2019a
      - ./CI/scripts/dockermake build
      - ./CI/scripts/dockermake add_libad9361
      - ./CI/scripts/dockermake gen_tlbx
@@ -31,7 +32,7 @@ build:master:
     stage: build
     script:
      - export HDLBRANCH=hdl_2018_r2
-     - export MLRELEASE=R2018b
+     - export MLRELEASE=R2019a
      - ./CI/scripts/dockermake build
      - export HDLBRANCH=
      - export MLRELEASE=
@@ -41,14 +42,15 @@ build:master:
             - hdl_wa_bsp/
 
 # Test HWA no install
-test:2018_R1:
+test:2018_R2:
     tags:
      - vivado
      - matlab
     stage: test
     dependencies:
-     - build:2018_R1
+     - build:2018_R2
     script:
+     - export MLRELEASE=R2019a
      - ./CI/scripts/dockermake test
      - ./CI/scripts/dockermake zip
     artifacts:
@@ -60,14 +62,15 @@ test:2018_R1:
             junit: test/BSPTestResults.xml
 
 # Test HWA with install
-test_installer:2018_R1_Installer:
+test_installer:2018_R2_Installer:
     tags:
      - vivado
      - matlab
     stage: test
     dependencies:
-     - build:2018_R1
+     - build:2018_R2
     script:
+     - export MLRELEASE=R2019a
      - cp mltbx/* .
      - pwd
      - ls
@@ -83,14 +86,15 @@ test_installer:2018_R1_Installer:
             junit: test/BSPTestResults.xml
 
 # Test HWA no install
-test:2018_R1:
+test:2018_R2:
     tags:
      - vivado
      - matlab
     stage: test
     dependencies:
-     - build:2018_R1
+     - build:2018_R2
     script:
+     - export MLRELEASE=R2019a
      - ./CI/scripts/dockermake test
      - ./CI/scripts/dockermake zip
     artifacts:
@@ -101,15 +105,34 @@ test:2018_R1:
         reports:
             junit: test/BSPTestResults.xml
 
+# Test weekly fully sythesized design
+test:Synthesize:
+    when: manual
+    tags:
+     - matlab
+     - vivado
+    stage: test
+    dependencies:
+     - build:2018_R2
+    script:
+     - ./CI/scripts/dockermake test_synth
+    artifacts:
+        when: always
+        name: "$CI_COMMIT_REF_NAME"
+        paths:
+            - test/
+            - Report.pdf
+
 # Test targeting demos (no hardware)
 test:targeting_demos:
     tags:
      - matlab
      - vivado
     stage: test
     dependencies:
-     - build:2018_R1
+     - build:2018_R2
     script:
+     - export MLRELEASE=R2019a
      - ./CI/scripts/dockermake test_targeting_demos
     artifacts:
         when: always
@@ -125,8 +148,9 @@ test_hardware:Streaming_Hardware:
      - hardware
     stage: test_hardware
     dependencies:
-     - build:2018_R1
+     - build:2018_R2
     script:
+     - export MLRELEASE=R2019a
      - cd CI/scripts
      - make test_streaming
     artifacts:
@@ -143,8 +167,9 @@ test_hardware:EVM_Hardware:
      - hardware
     stage: test_hardware
     dependencies:
-     - build:2018_R1
+     - build:2018_R2
     script:
+     - export MLRELEASE=R2019a
      - cd CI/scripts
      - make test_evm
     artifacts:
@@ -158,8 +183,8 @@ deploy:
      - matlab
     stage: deploy
     dependencies:
-     - test:2018_R1
-     - test_installer:2018_R1_Installer
+     - test:2018_R2
+     - test_installer:2018_R2_Installer
     script:
      - echo "Complete"
     artifacts:

CI/projects/adrv9361z7035/ccbob_cmos/system_bd.tcl

@@ -1,6 +1,6 @@
 
-source $ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_bd.tcl
-source $ad_hdl_dir/projects/adrv9361z7035/common/ccbob_bd.tcl
+source ../common/adrv9361z7035_bd.tcl
+source ../common/ccbob_bd.tcl
 
 ad_ip_parameter util_ad9361_divclk CONFIG.SEL_0_DIV 2
 ad_ip_parameter util_ad9361_divclk CONFIG.SEL_1_DIV 1
@@ -9,5 +9,3 @@ cfg_ad9361_interface CMOS
 
 ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 29
 
-
-

CI/projects/adrv9361z7035/ccbob_cmos/system_project_rx.tcl

@@ -14,7 +14,6 @@ adi_project_files adrv9361z7035_ccbob_cmos [list \
   "$ad_hdl_dir/projects/adrv9361z7035/common/ccbob_constr.xdc" \
   "system_top.v" ]
 
-set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
 adi_project_run adrv9361z7035_ccbob_cmos
 #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl
 # Copy the boot file to the root directory

CI/projects/adrv9361z7035/ccbob_cmos/system_project_rx_tx.tcl

@@ -14,7 +14,6 @@ adi_project_files adrv9361z7035_ccbob_cmos [list \
   "$ad_hdl_dir/projects/adrv9361z7035/common/ccbob_constr.xdc" \
   "system_top.v" ]
 
-set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
 adi_project_run adrv9361z7035_ccbob_cmos
 #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl
 # Copy the boot file to the root directory

CI/projects/adrv9361z7035/ccbob_cmos/system_project_tx.tcl

@@ -14,7 +14,6 @@ adi_project_files adrv9361z7035_ccbob_cmos [list \
   "$ad_hdl_dir/projects/adrv9361z7035/common/ccbob_constr.xdc" \
   "system_top.v" ]
 
-set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
 adi_project_run adrv9361z7035_ccbob_cmos
 #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl
 # Copy the boot file to the root directory

CI/projects/adrv9361z7035/ccbob_cmos/system_top.v

@@ -8,7 +8,7 @@
 // terms.
 //
 // The user should read each of these license terms, and understand the
-// freedoms and responsabilities that he or she has by using this source/core.
+// freedoms and responsibilities that he or she has by using this source/core.
 //
 // This core is distributed in the hope that it will be useful, but WITHOUT ANY
 // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
@@ -188,6 +188,7 @@ module system_top (
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),
+    .gps_pps (1'b0),
     .gt_ref_clk (gt_ref_clk),
     .gt_rx_n (gt_rx_n),
     .gt_rx_p (gt_rx_p),
@@ -196,18 +197,6 @@ module system_top (
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .otg_vbusoc (1'b0),
-    .ps_intr_00 (1'b0),
-    .ps_intr_01 (1'b0),
-    .ps_intr_02 (1'b0),
-    .ps_intr_03 (1'b0),
-    .ps_intr_04 (1'b0),
-    .ps_intr_05 (1'b0),
-    .ps_intr_06 (1'b0),
-    .ps_intr_07 (1'b0),
-    .ps_intr_08 (1'b0),
-    .ps_intr_09 (1'b0),
-    .ps_intr_10 (1'b0),
-    .ps_intr_15 (1'b0),
     .rx_clk_in (rx_clk_in),
     .rx_data_in (rx_data_in),
     .rx_frame_in (rx_frame_in),

CI/projects/adrv9361z7035/ccbob_lvds/system_bd.tcl

@@ -1,6 +1,6 @@
 
-source $ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_bd.tcl
-source $ad_hdl_dir/projects/adrv9361z7035/common/ccbob_bd.tcl
+source ../common/adrv9361z7035_bd.tcl
+source ../common/ccbob_bd.tcl
 
 cfg_ad9361_interface LVDS
 

CI/projects/adrv9361z7035/ccbob_lvds/system_project_rx.tcl

@@ -14,7 +14,6 @@ adi_project_files adrv9361z7035_ccbob_lvds [list \
   "$ad_hdl_dir/projects/adrv9361z7035/common/ccbob_constr.xdc" \
   "system_top.v" ]
 
-set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
 adi_project_run adrv9361z7035_ccbob_lvds
 #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl
 # Copy the boot file to the root directory

CI/projects/adrv9361z7035/ccbob_lvds/system_project_rx_tx.tcl

@@ -14,7 +14,6 @@ adi_project_files adrv9361z7035_ccbob_lvds [list \
   "$ad_hdl_dir/projects/adrv9361z7035/common/ccbob_constr.xdc" \
   "system_top.v" ]
 
-set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
 adi_project_run adrv9361z7035_ccbob_lvds
 #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl
 # Copy the boot file to the root directory

CI/projects/adrv9361z7035/ccbob_lvds/system_project_tx.tcl

@@ -14,7 +14,6 @@ adi_project_files adrv9361z7035_ccbob_lvds [list \
   "$ad_hdl_dir/projects/adrv9361z7035/common/ccbob_constr.xdc" \
   "system_top.v" ]
 
-set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
 adi_project_run adrv9361z7035_ccbob_lvds
 #source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl
 # Copy the boot file to the root directory

CI/projects/adrv9361z7035/ccbob_lvds/system_top.v

@@ -8,7 +8,7 @@
 // terms.
 //
 // The user should read each of these license terms, and understand the
-// freedoms and responsabilities that he or she has by using this source/core.
+// freedoms and responsibilities that he or she has by using this source/core.
 //
 // This core is distributed in the hope that it will be useful, but WITHOUT ANY
 // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
@@ -192,6 +192,7 @@ module system_top (
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),
+    .gps_pps (1'b0),
     .gt_ref_clk (gt_ref_clk),
     .gt_rx_n (gt_rx_n),
     .gt_rx_p (gt_rx_p),
@@ -200,18 +201,6 @@ module system_top (
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .otg_vbusoc (1'b0),
-    .ps_intr_00 (1'b0),
-    .ps_intr_01 (1'b0),
-    .ps_intr_02 (1'b0),
-    .ps_intr_03 (1'b0),
-    .ps_intr_04 (1'b0),
-    .ps_intr_05 (1'b0),
-    .ps_intr_06 (1'b0),
-    .ps_intr_07 (1'b0),
-    .ps_intr_08 (1'b0),
-    .ps_intr_09 (1'b0),
-    .ps_intr_10 (1'b0),
-    .ps_intr_15 (1'b0),
     .rx_clk_in_n (rx_clk_in_n),
     .rx_clk_in_p (rx_clk_in_p),
     .rx_data_in_n (rx_data_in_n),

CI/projects/adrv9361z7035/ccbox_lvds/system_bd.tcl

@@ -1,10 +1,11 @@
 
-source $ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_bd.tcl
-source $ad_hdl_dir/projects/adrv9361z7035/common/ccbox_bd.tcl
+source ../common/adrv9361z7035_bd.tcl
+source ../common/ccbox_bd.tcl
 
 cfg_ad9361_interface LVDS
 
-set_property CONFIG.ADC_INIT_DELAY 29 [get_bd_cells axi_ad9361]
-
+create_bd_port -dir O sys_cpu_clk_out
+ad_connect  sys_cpu_clk sys_cpu_clk_out
 
+set_property CONFIG.ADC_INIT_DELAY 29 [get_bd_cells axi_ad9361]