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Re-PR add stm32h755II chip #12394

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Merged
xiaoxiang781216 merged 1 commit into from
Jun 12, 2024
Merged

Re-PR add stm32h755II chip #12394

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23 changes: 23 additions & 0 deletions arch/arm/src/stm32h7/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -284,11 +284,34 @@ config STM32H7_HAVE_SMPS
bool
default n

config STM32H7_HAVE_PWR_DIRECT_SMPS_SUPPLY
bool
default n

config STM32H7_PWR_DIRECT_SMPS_SUPPLY
bool "Use direct SMPS supply mode"
depends on STM32H7_HAVE_SMPS
default n

choice
prompt "STM32 H7 Power Supply Selection"
default STM32H7_PWR_DEFAULT_SUPPLY
depends on STM32H7_HAVE_SMPS && !STM32H7_HAVE_PWR_DIRECT_SMPS_SUPPLY
---help---
The STM32H7x5 and STM32H7x7 support power supply configrations for the VCORE core domain and an external supply,
by configuring the SMPS step-down converter and voltage regulator.
Note:The SMPS step-down converter is not available on all packages.

Currenlty the only supported modes are Direct SMPS supply and LDO supply.

config STM32H7_PWR_DEFAULT_SUPPLY
bool "Default"

config STM32H7_PWR_LDO_SUPPLY
bool "Use LDO supply mode"

endchoice # "STM32 H7 Power Supply Selection"

config STM32H7_IO_CONFIG_A
bool
default n
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20 changes: 11 additions & 9 deletions arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h
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Expand Up @@ -129,16 +129,18 @@

#define STM32_PWR_CR3_BYPASS (1 << 0) /* Bit 0: Power management unit bypass */
#define STM32_PWR_CR3_LDOEN (1 << 1) /* Bit 1: Low drop-out regulator enable */
#define STM32_PWR_CR3_SCUEN (1 << 2) /* Bit 2: Supply configuration update enable */
#ifndef CONFIG_STM32H7_HAVE_SMPS
# define STM32_PWR_CR3_SCUEN (1 << 2) /* Bit 2: Supply configuration update enable */
#endif
#ifdef CONFIG_STM32H7_HAVE_SMPS
#define STM32_PWR_CR3_SDEN (1 << 2) /* Bit 2: SMPS step-down converter enable */
#define STM32_PWR_CR3_SMPSEXTHP (1 << 3) /* Bit 3: SMPS step-down converter external power delivery selection */
#define STM32_PWR_CR3_SMPSLEVEL_SHIFT (4) /* BitS 4-5: SMPS step-down converter voltage output level selection */
# define STM32_PWR_CR3_SMPSLEVEL_MASK (3 << STM32_PWR_CR3_SMPSLEVEL_SHIFT)
# define STM32_PWR_CR3_SMPSLEVEL_R (0 << STM32_PWR_CR3_SMPSLEVEL_SHIFT) /* 00: */
# define STM32_PWR_CR3_SMPSLEVEL_1V8 (1 << STM32_PWR_CR3_SMPSLEVEL_SHIFT) /* 01 */
# define STM32_PWR_CR3_SMPSLEVEL_2V5 (2 << STM32_PWR_CR3_SMPSLEVEL_SHIFT) /* 10: */
# define STM32_PWR_CR3_SMPSLEVEL_2V5B (3 << STM32_PWR_CR3_SMPSLEVEL_SHIFT) /* 11: */
# define STM32_PWR_CR3_SDEN (1 << 2) /* Bit 2: SMPS step-down converter enable */
# define STM32_PWR_CR3_SMPSEXTHP (1 << 3) /* Bit 3: SMPS step-down converter external power delivery selection */
# define STM32_PWR_CR3_SMPSLEVEL_SHIFT (4) /* BitS 4-5: SMPS step-down converter voltage output level selection */
# define STM32_PWR_CR3_SMPSLEVEL_MASK (3 << STM32_PWR_CR3_SMPSLEVEL_SHIFT)
# define STM32_PWR_CR3_SMPSLEVEL_R (0 << STM32_PWR_CR3_SMPSLEVEL_SHIFT) /* 00: */
# define STM32_PWR_CR3_SMPSLEVEL_1V8 (1 << STM32_PWR_CR3_SMPSLEVEL_SHIFT) /* 01 */
# define STM32_PWR_CR3_SMPSLEVEL_2V5 (2 << STM32_PWR_CR3_SMPSLEVEL_SHIFT) /* 10: */
# define STM32_PWR_CR3_SMPSLEVEL_2V5B (3 << STM32_PWR_CR3_SMPSLEVEL_SHIFT) /* 11: */
#endif
/* Bits 6-7: Reserved */
#define STM32_PWR_CR3_VBE (1 << 8) /* Bit 8: VBAT charging enable */
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6 changes: 1 addition & 5 deletions arch/arm/src/stm32h7/stm32_rcc.c
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Expand Up @@ -59,11 +59,7 @@
#elif defined(CONFIG_STM32H7_STM32H7B3XX)
# include "stm32h7x3xx_rcc.c"
#elif defined(CONFIG_STM32H7_STM32H7X5XX)
# if defined(CONFIG_ARCH_CHIP_STM32H755II)
# include "stm32h7x5xx_rcc.c"
# else
# include "stm32h7x3xx_rcc.c"
# endif
# include "stm32h7x3xx_rcc.c"
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
# include "stm32h7x7xx_rcc.c"
#else
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35 changes: 26 additions & 9 deletions arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
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Expand Up @@ -133,6 +133,30 @@
# endif
#endif

/* When the SoC supports SMPS we currently support 2 configurations:
* Direct SMP Supply OR LDO only supply.
*
* When the Soc does not supports SMPS we support only the LDO supply.
*/

#ifdef CONFIG_STM32H7_HAVE_SMPS
# define STM32_PWR_CR3_MASK ~(STM32_PWR_CR3_BYPASS | \
STM32_PWR_CR3_LDOEN | \
STM32_PWR_CR3_SDEN | \
STM32_PWR_CR3_SMPSEXTHP | \
STM32_PWR_CR3_SMPSLEVEL_MASK)

# if defined(CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY)
# define STM32_PWR_CR3_SELECTION STM32_PWR_CR3_SDEN
# else
# define STM32_PWR_CR3_SELECTION STM32_PWR_CR3_LDOEN
# endif
#else
# define STM32_PWR_CR3_MASK 0xffffffff
# define STM32_PWR_CR3_SELECTION (STM32_PWR_CR3_LDOEN | STM32_PWR_CR3_SCUEN)

#endif

/****************************************************************************
* Private Functions
****************************************************************************/
Expand Down Expand Up @@ -880,17 +904,10 @@ void stm32_stdclockconfig(void)
* N.B. The system shall be power cycled before writing a new value.
*/

#if defined(CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY)
regval = getreg32(STM32_PWR_CR3);
regval &= ~(STM32_PWR_CR3_BYPASS | STM32_PWR_CR3_LDOEN |
STM32_PWR_CR3_SMPSEXTHP | STM32_PWR_CR3_SMPSLEVEL_MASK);
regval |= STM32_PWR_CR3_SCUEN;
regval &= STM32_PWR_CR3_MASK;
regval |= STM32_PWR_CR3_SELECTION;
putreg32(regval, STM32_PWR_CR3);
#else
regval = getreg32(STM32_PWR_CR3);
regval |= STM32_PWR_CR3_LDOEN | STM32_PWR_CR3_SCUEN;
putreg32(regval, STM32_PWR_CR3);
#endif

/* Set the voltage output scale */

Expand Down
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