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arch/arm/stm32l5: enable LPUART1 console on ST-Link VCP. on nucleo-l552ze board#18526

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xiaoxiang781216 merged 1 commit intoapache:masterfrom
anjiahao1:stm32l5-lpuart1-vcp
Mar 11, 2026
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arch/arm/stm32l5: enable LPUART1 console on ST-Link VCP. on nucleo-l552ze board#18526
xiaoxiang781216 merged 1 commit intoapache:masterfrom
anjiahao1:stm32l5-lpuart1-vcp

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Summary

  • The Nucleo-L552ZE-Q board ships with LPUART1 (PG7/PG8) connected to the ST-Link virtual COM port by default, but the NuttX BSP only supported USART3 which requires an external TTL adapter. This change enables LPUART1 as the default NSH console so the board works out-of-the-box with the built-in VCP.
  • Three bugs prevented LPUART1 from working:
    1. stm32l5_lowputc: Missing LPUART-specific BRR formula. LPUART uses BRR = 256 * fCK / baud instead of the standard USART divisor.
    2. stm32_boot: LPUART1 pins PG7/PG8 are on GPIOG which is powered by VDDIO2. The low-level GPIO setup in stm32l5_lowsetup() runs before VDDIO2 is enabled, so GPIOG writes silently fail. Added VDDIO2 enable and GPIO reconfiguration in stm32l5_board_initialize().
    3. stm32l5_serial: LPUART1 apbclock was incorrectly set to PCLK2 (should be PCLK1 per RCC_APB1ENR2), and the runtime setformat() lacked an LPUART BRR branch. Also cast to uint64_t to prevent 32-bit overflow in (fCK << 8).
  • The nsh defconfig is switched from USART3 to LPUART1, GPIO_LPUART1 pin definitions are added to board.h, and board documentation is updated.

Impact

  • Is new feature added? YES — LPUART1 serial driver support for STM32L5 Nucleo-L552ZE-Q.
  • Impact on user? YES — The default nsh console is now on LPUART1 (ST-Link VCP) instead of USART3. Users who rely on USART3 need to reconfigure.
  • Impact on build? NO.
  • Impact on hardware? YES — STM32L5 arch serial driver and Nucleo-L552ZE board BSP are changed.
  • Impact on documentation? YES — Board documentation updated to reflect LPUART1 as default console.
  • Impact on security? NO.
  • Impact on compatibility? YES — Existing users of nucleo-l552ze:nsh who use USART3 with external adapter will need to switch defconfig back. The USART3 configuration is documented.

Testing

I confirm that changes are verified on local setup and works as intended:

  • Build Host(s): Ubuntu 24.04 x86_64, arm-none-eabi-gcc 12.2.1
  • Target(s): Nucleo-L552ZE-Q real hardware with ST-Link VCP

Testing logs before change:

N/A — LPUART1 was not functional before this change. NSH console was only available on USART3 with external TTL adapter.

Testing logs after change:

$ picocom -b 115200 /dev/ttyACM0

NuttShell (NSH) NuttX-12.8.0
nsh>

Verified via GDB/OpenOCD register inspection:

  • LPUART1_BRR = 0x3BADC (correct: 256 × 110MHz / 115200)
  • GPIOG_MODER PG7/PG8 = AF mode
  • GPIOG_AFRL/AFRH = AF8

PR verification Self-Check

  • This PR introduces only one functional change.
  • I have updated all required description fields above.
  • My PR adheres to Contributing Guidelines and Documentation (git commit title and message, coding standard, etc).
  • My PR is still work in progress (not ready for review).
  • My PR is ready for review and can be safely merged into a codebase.

@github-actions github-actions bot added Area: Documentation Improvements or additions to documentation Arch: arm Issues related to ARM (32-bit) architecture Size: M The size of the change in this PR is medium Board: arm labels Mar 11, 2026
@anjiahao1 anjiahao1 force-pushed the stm32l5-lpuart1-vcp branch from 051c55d to 12b14f7 Compare March 11, 2026 06:13
jerpelea
jerpelea previously approved these changes Mar 11, 2026
@jerpelea jerpelea changed the title stm32l5/nucleo-l552ze: enable LPUART1 console on ST-Link VCP. arch/arm/stm32l5: enable LPUART1 console on ST-Link VCP. on nucleo-l552ze board Mar 11, 2026
Three fixes to make LPUART1 work as NSH console on Nucleo-L552ZE-Q:

1. stm32l5_lowputc: add LPUART-specific BRR formula (256 * fCK / baud)
   instead of reusing the standard USART divisor calculation.

2. stm32_boot: enable VDDIO2 and reconfigure LPUART1 GPIOs (PG7/PG8)
   in board_initialize. The low-level setup runs before VDDIO2 is
   enabled, so GPIOG writes silently fail.

3. stm32l5_serial: fix LPUART1 apbclock (PCLK1 not PCLK2), add
   LPUART BRR branch in setformat, cast to uint64_t to prevent
   32-bit overflow in (fCK << 8).

Also switch nsh defconfig from USART3 to LPUART1, add GPIO_LPUART1
pin definitions in board.h, and update board documentation.

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
@anjiahao1 anjiahao1 dismissed stale reviews from xiaoxiang781216 and jerpelea via 1bb8dfd March 11, 2026 08:32
@anjiahao1 anjiahao1 force-pushed the stm32l5-lpuart1-vcp branch from 12b14f7 to 1bb8dfd Compare March 11, 2026 08:32
@xiaoxiang781216 xiaoxiang781216 merged commit 718ae3d into apache:master Mar 11, 2026
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Arch: arm Issues related to ARM (32-bit) architecture Area: Documentation Improvements or additions to documentation Board: arm Size: M The size of the change in this PR is medium

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