tricore: Add fpu init and fpucmp support.#18908
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xiaoxiang781216
previously approved these changes
May 20, 2026
Initialize the FPU and enable the FZ (flush-to-zero) trap for TriCore TC4xx processors. This ensures floating-point divide-by-zero exceptions are properly caught and reported via the trap handler. Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
Implement up_fpucmp to compare FPU register state between two saved contexts. This is used by the ostest FPU test to verify that FPU registers are properly preserved across context switches. Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
up_fpucmp was comparing lower CSA registers (offset 0) using upper CSA register definitions (REG_D8-D15). Since up_saveusercontext stores: - Lower CSA at saveregs[0..15] - Upper CSA at saveregs[16..31] The fix adds TC_CONTEXT_REGS offset to point to the upper CSA and compares only D8-D15 which are the FPU data registers on TriCore. Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
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linguini1
approved these changes
May 20, 2026
xiaoxiang781216
approved these changes
May 21, 2026
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Summary
Impact
Testing
I confirm that changes are verified on local setup and works as intended:
Testing logs (runtime, ostest FPU on TC4D9 EVB):