arch/tricore: Improve up_backtrace implementation#18910
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@zyfeier please fix the conflict |
1. Make tricore_backtrace.c conditional on CONFIG_SCHED_BACKTRACE, consistent with RISC-V and ARM architectures. 2. Add NULL return address check to terminate early on invalid entries. 3. Fix non-current task backtrace to use regs[REG_LPCXI] which preserves the UL bit needed for correct CSA type identification. Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
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linguini1
approved these changes
May 20, 2026
xiaoxiang781216
approved these changes
May 21, 2026
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Summary
Improve the existing TriCore
up_backtrace()implementation (merged in #18899):tricore_backtrace.cconditional onCONFIG_SCHED_BACKTRACE, consistent with RISC-V and ARM architectures.csa[REG_UA11] == 0to avoid invalid entries.regs[REG_LPCXI]instead oftricore_addr2csa(tcb->xcp.regs)to preserve the UL bit needed for correct CSA type identification.Testing
Verified on TC4D9 EVB (triboard_tc4x9_com:nsh) with
CONFIG_SCHED_BACKTRACE=y:Exiting with status 0)addr2line verification:
Call chain is correct. User-space functions (
hello_main/func_a/func_b/func_c) are not in backtrace because the compiler optimized them into tail-jumps (jinstead ofcall), which is expected TriCore behavior — onlycallinstructions save Upper CSA.