arch/armv7ar: use robust code sequences for cache maintenance#9047
Merged
xiaoxiang781216 merged 1 commit intoapache:masterfrom Apr 25, 2023
Merged
arch/armv7ar: use robust code sequences for cache maintenance#9047xiaoxiang781216 merged 1 commit intoapache:masterfrom
xiaoxiang781216 merged 1 commit intoapache:masterfrom
Conversation
Contributor
|
@zyfeier please rebase your change. |
Invalidate operations at DDI0246H_l2c310_r3p3_trm: If there is a stale entry in the L2 cache, the system enables the invalidation of the L1 cache. But before the controller invalidates the L2 cache, it allocates a line from the L2 cache to an L1 cache. The robust code sequence for invalidation with a non-exclusive cache arrangement is: 1. InvalLevel2 Address ; forces the address out past level 2 2. CACHE SYNC ; Ensures completion of the L2 inval 3. InvalLevel1 Address ; This is broadcast within the cluster 4. DSB ; Ensure completion of the inval as far as Level 2. This sequence ensures that, if there is an allocation to L1 after the L1 invalidation, the data picked up is the new data and not stale data from the L2 Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Contributor
@zyfeier |
Contributor
Author
Yes, test with sabre-6quad board and our bes2003 board. |
masayuki2009
approved these changes
Apr 25, 2023
xiaoxiang781216
approved these changes
Apr 25, 2023
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
4 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Summary
Invalidate operations at DDI0246H_l2c310_r3p3_trm:
If there is a stale entry in the L2 cache, the system enables the invalidation of the L1 cache. But before the controller invalidates the L2 cache, it allocates a line from the L2 cache to an L1 cache.
The robust code sequence for invalidation with a non-exclusive cache arrangement is:
This sequence ensures that, if there is an allocation to L1 after the L1 invalidation, the data picked up is the new data and not stale data from the L2.
Impact
L2 cache
Testing
sabre-6quad:smp