apache · xiaoxiang781216 · Jul 13, 2023 · Jul 13, 2023
@@ -147,29 +147,29 @@ typedef struct
   uint32_t control;           /* Transfer control */
 } dmac_lli_t;
 
-#define CXD56_DMAC_M2M   0  /**< Memory to memory */
-#define CXD56_DMAC_M2P   1  /**< Memory to peripheral, DMAC controlled */
-#define CXD56_DMAC_P2M   2  /**< Peripheral to memory, DMAC controlled */
-#define CXD56_DMAC_P2P   3  /**< Peripheral to peripheral */
-#define CXD56_DMAC_P2CP  4  /**< P2P destination controlled */
-#define CXD56_DMAC_M2CP  5  /**< M2P peripheral controlled */
-#define CXD56_DMAC_CP2M  6  /**< P2M peripheral controlled */
-#define CXD56_DMAC_CP2P  7  /**< P2P source controlled */
-
-#define CXD56_DMAC_BSIZE1    0     /**< 1 burst */
-#define CXD56_DMAC_BSIZE4    1     /**< 4 burst */
-#define CXD56_DMAC_BSIZE8    2     /**< 8 burst */
-#define CXD56_DMAC_BSIZE16   3     /**< 16 burst */
-#define CXD56_DMAC_BSIZE32   4     /**< 32 burst */
-#define CXD56_DMAC_BSIZE64   5     /**< 64 burst */
-#define CXD56_DMAC_BSIZE128  6     /**< 128 burst */
-#define CXD56_DMAC_BSIZE256  7     /**< 256 burst */
-
-#define CXD56_DMAC_LITTLE_ENDIAN  0  /**< Little endian */
-#define CXD56_DMAC_BIG_ENDIAN     1  /**< Bit endian */
-
-#define CXD56_DMAC_MASTER1 0 /**< AHB master 1 */
-#define CXD56_DMAC_MASTER2 1 /**< AHB master 2 */
+#define CXD56_DMAC_M2M   0  /* Memory to memory */
+#define CXD56_DMAC_M2P   1  /* Memory to peripheral, DMAC controlled */
+#define CXD56_DMAC_P2M   2  /* Peripheral to memory, DMAC controlled */
+#define CXD56_DMAC_P2P   3  /* Peripheral to peripheral */
+#define CXD56_DMAC_P2CP  4  /* P2P destination controlled */
+#define CXD56_DMAC_M2CP  5  /* M2P peripheral controlled */
+#define CXD56_DMAC_CP2M  6  /* P2M peripheral controlled */
+#define CXD56_DMAC_CP2P  7  /* P2P source controlled */
+
+#define CXD56_DMAC_BSIZE1    0     /* 1 burst */
+#define CXD56_DMAC_BSIZE4    1     /* 4 burst */
+#define CXD56_DMAC_BSIZE8    2     /* 8 burst */
+#define CXD56_DMAC_BSIZE16   3     /* 16 burst */
+#define CXD56_DMAC_BSIZE32   4     /* 32 burst */
+#define CXD56_DMAC_BSIZE64   5     /* 64 burst */
+#define CXD56_DMAC_BSIZE128  6     /* 128 burst */
+#define CXD56_DMAC_BSIZE256  7     /* 256 burst */
+
+#define CXD56_DMAC_LITTLE_ENDIAN  0  /* Little endian */
+#define CXD56_DMAC_BIG_ENDIAN     1  /* Bit endian */
+
+#define CXD56_DMAC_MASTER1 0 /* AHB master 1 */
+#define CXD56_DMAC_MASTER2 1 /* AHB master 2 */
 
 /* max transfer size at a time */
 

@@ -41,12 +41,12 @@
 #define CXD56_DMA_PERIPHERAL_SPI5_TX  (4)
 #define CXD56_DMA_PERIPHERAL_SPI5_RX  (5)
 
-#define CXD56_DMA_INTR_ITC (1u<<0) /**< Terminal count interrupt status */
-#define CXD56_DMA_INTR_ERR (1u<<1) /**< Error interrupt status */
+#define CXD56_DMA_INTR_ITC (1u<<0) /* Terminal count interrupt status */
+#define CXD56_DMA_INTR_ERR (1u<<1) /* Error interrupt status */
 
-#define CXD56_DMAC_WIDTH8   0      /**< 8 bit width */
-#define CXD56_DMAC_WIDTH16  1      /**< 16 bit width */
-#define CXD56_DMAC_WIDTH32  2      /**< 32 bit width */
+#define CXD56_DMAC_WIDTH8   0      /* 8 bit width */
+#define CXD56_DMAC_WIDTH16  1      /* 16 bit width */
+#define CXD56_DMAC_WIDTH32  2      /* 32 bit width */
 
 /****************************************************************************
  * Public Types

@@ -200,8 +200,8 @@
   #define g_pLLcteQSample _symrom_g_pLLcteQSample
   #define g_pmCounters _symrom_g_pmCounters
   #define g_pPeriodicAdvInfo _symrom_g_pPeriodicAdvInfo
-  #define ll_isIrkAllZero	_symrom_ll_isIrkAllZero
-  #define g_currentLocalAddrType	_symrom_g_currentLocalAddrType
+  #define ll_isIrkAllZero _symrom_ll_isIrkAllZero
+  #define g_currentLocalAddrType _symrom_g_currentLocalAddrType
   #define g_rfPhyClkSel _symrom_g_rfPhyClkSel
   #define g_rfPhyDtmCmd _symrom_g_rfPhyDtmCmd
   #define g_rfPhyDtmEvt _symrom_g_rfPhyDtmEvt

@@ -36,15 +36,15 @@
 
 /* TWI register offsets *****************************************************/
 
-#define A64_TWI_ADDR_OFFSET    	    (0x00)  /* 31:8 bit reserved,7-1 bit for slave addr,0 bit for GCE */
-#define A64_TWI_XADDR_OFFSET   	    (0x04)  /* 31:8 bit reserved,7-0 bit for second addr in 10bit addr */
-#define A64_TWI_DATA_OFFSET    	    (0x08)  /* 31:8 bit reserved,7-0 bit send or receive data byte */
+#define A64_TWI_ADDR_OFFSET         (0x00)  /* 31:8 bit reserved,7-1 bit for slave addr,0 bit for GCE */
+#define A64_TWI_XADDR_OFFSET        (0x04)  /* 31:8 bit reserved,7-0 bit for second addr in 10bit addr */
+#define A64_TWI_DATA_OFFSET         (0x08)  /* 31:8 bit reserved,7-0 bit send or receive data byte */
 #define A64_TWI_CNTR_OFFSET         (0x0c)  /* 31:8 bit reserved, INT_EN, BUS_EN, M_STA, INT_FLAG, A_ACK */
-#define A64_TWI_STAT_OFFSET    	    (0x10) 	/* 28 interrupt types + 0xF8 normal type = 29 */
-#define A64_TWI_CCR_OFFSET     	    (0x14) 	/* 31:7 bit reserved,6-3bit,CLK_M,2-0bit CLK_N */
-#define A64_TWI_SRST_OFFSET    	    (0x18) 	/* 31:1 bit reserved;0bit,write 1 to clear 0. */
-#define A64_TWI_EFR_OFFSET     	    (0x1c)  /* 31:2 bit reserved,1:0 bit data byte follow read comand */
-#define A64_TWI_LCR_OFFSET     	    (0x20) 	/* 31:6 bits reserved  5:0 bit for sda&scl control*/
+#define A64_TWI_STAT_OFFSET         (0x10)  /* 28 interrupt types + 0xF8 normal type = 29 */
+#define A64_TWI_CCR_OFFSET          (0x14)  /* 31:7 bit reserved,6-3bit,CLK_M,2-0bit CLK_N */
+#define A64_TWI_SRST_OFFSET         (0x18)  /* 31:1 bit reserved;0bit,write 1 to clear 0. */
+#define A64_TWI_EFR_OFFSET          (0x1c)  /* 31:2 bit reserved,1:0 bit data byte follow read comand */
+#define A64_TWI_LCR_OFFSET          (0x20)  /* 31:6 bits reserved  5:0 bit for sda&scl control*/
 #define A64_TWI_DVFS_OFFSET         (0x24)  /* 31:3 bits reserved  2:0 bit for dvfs control. only A10 support */
 
 /* TWI register addresses ***************************************************/
@@ -93,8 +93,8 @@
 
 /* TWI address register */
 
-#define TWI_GCE_EN      	(0x1<<0)  /* general call address enable for slave mode */
-#define TWI_ADDR_MASK   	(0x7f<<1) /* 7:1 bits */
+#define TWI_GCE_EN      (0x1<<0)  /* general call address enable for slave mode */
+#define TWI_ADDR_MASK   (0x7f<<1) /* 7:1 bits */
 
 /* TWI extend address register */
 
@@ -150,21 +150,21 @@
 
 /* 7:0 bits use only,default is 0xF8 */
 
-#define TWI_STAT_BUS_ERR        (0x00) 	/* BUS ERROR */
+#define TWI_STAT_BUS_ERR        (0x00) /* BUS ERROR */
 
 /* Master mode use only */
 
-#define TWI_STAT_TX_STA     (0x08) 	/* START condition transmitted */
-#define TWI_STAT_TX_RESTA   (0x10) 	/* Repeated START condition transmitted */
-#define TWI_STAT_TX_AW_ACK  (0x18) 	/* Address+Write bit transmitted, ACK received */
-#define TWI_STAT_TX_AW_NAK  (0x20) 	/* Address+Write bit transmitted, ACK not received */
-#define TWI_STAT_TXD_ACK    (0x28) 	/* data byte transmitted in master mode,ack received */
-#define TWI_STAT_TXD_NAK    (0x30) 	/* data byte transmitted in master mode ,ack not received */
-#define TWI_STAT_ARBLOST    (0x38) 	/* arbitration lost in address or data byte */
-#define TWI_STAT_TX_AR_ACK  (0x40) 	/* Address+Read bit transmitted, ACK received */
-#define TWI_STAT_TX_AR_NAK  (0x48) 	/* Address+Read bit transmitted, ACK not received */
-#define TWI_STAT_RXD_ACK    (0x50) 	/* data byte received in master mode ,ack transmitted */
-#define TWI_STAT_RXD_NAK    (0x58) 	/* date byte received in master mode,not ack transmitted */
+#define TWI_STAT_TX_STA     (0x08)  /* START condition transmitted */
+#define TWI_STAT_TX_RESTA   (0x10)  /* Repeated START condition transmitted */
+#define TWI_STAT_TX_AW_ACK  (0x18)  /* Address+Write bit transmitted, ACK received */
+#define TWI_STAT_TX_AW_NAK  (0x20)  /* Address+Write bit transmitted, ACK not received */
+#define TWI_STAT_TXD_ACK    (0x28)  /* data byte transmitted in master mode,ack received */
+#define TWI_STAT_TXD_NAK    (0x30)  /* data byte transmitted in master mode ,ack not received */
+#define TWI_STAT_ARBLOST    (0x38)  /* arbitration lost in address or data byte */
+#define TWI_STAT_TX_AR_ACK  (0x40)  /* Address+Read bit transmitted, ACK received */
+#define TWI_STAT_TX_AR_NAK  (0x48)  /* Address+Read bit transmitted, ACK not received */
+#define TWI_STAT_RXD_ACK    (0x50)  /* data byte received in master mode ,ack transmitted */
+#define TWI_STAT_RXD_NAK    (0x58)  /* date byte received in master mode,not ack transmitted */
 
 /* Slave mode use only */
 

@@ -36,9 +36,9 @@
 #define CONFIG_ARM_TIMER_VIRTUAL_IRQ        (GIC_PPI_INT_BASE + 11)
 #define CONFIG_ARM_TIMER_HYP_IRQ            (GIC_PPI_INT_BASE + 10)
 
-#define ARM_ARCH_TIMER_IRQ	CONFIG_ARM_TIMER_VIRTUAL_IRQ
-#define ARM_ARCH_TIMER_PRIO	IRQ_DEFAULT_PRIORITY
-#define ARM_ARCH_TIMER_FLAGS	IRQ_TYPE_LEVEL
+#define ARM_ARCH_TIMER_IRQ     CONFIG_ARM_TIMER_VIRTUAL_IRQ
+#define ARM_ARCH_TIMER_PRIO    IRQ_DEFAULT_PRIORITY
+#define ARM_ARCH_TIMER_FLAGS   IRQ_TYPE_LEVEL
 
 /****************************************************************************
  * Public Function Prototypes

@@ -43,14 +43,14 @@ extern "C"
  * Pre-processor Macros
  ****************************************************************************/
 
-#define ESP32C3_ERR_MPI_FILE_IO_ERROR           -0x0002  /**< An error occurred while reading from or writing to a file. */
-#define ESP32C3_ERR_MPI_BAD_INPUT_DATA          -0x0004  /**< Bad input parameters to function. */
-#define ESP32C3_ERR_MPI_INVALID_CHARACTER       -0x0006  /**< There is an invalid character in the digit string. */
-#define ESP32C3_ERR_MPI_BUFFER_TOO_SMALL        -0x0008  /**< The buffer is too small to write to. */
-#define ESP32C3_ERR_MPI_NEGATIVE_VALUE          -0x000A  /**< The input arguments are negative or result in illegal output. */
-#define ESP32C3_ERR_MPI_DIVISION_BY_ZERO        -0x000C  /**< The input argument for division is zero, which is not allowed. */
-#define ESP32C3_ERR_MPI_NOT_ACCEPTABLE          -0x000E  /**< The input arguments are not acceptable. */
-#define ESP32C3_ERR_MPI_ALLOC_FAILED            -0x0010  /**< Memory allocation failed. */
+#define ESP32C3_ERR_MPI_FILE_IO_ERROR           -0x0002  /* An error occurred while reading from or writing to a file. */
+#define ESP32C3_ERR_MPI_BAD_INPUT_DATA          -0x0004  /* Bad input parameters to function. */
+#define ESP32C3_ERR_MPI_INVALID_CHARACTER       -0x0006  /* There is an invalid character in the digit string. */
+#define ESP32C3_ERR_MPI_BUFFER_TOO_SMALL        -0x0008  /* The buffer is too small to write to. */
+#define ESP32C3_ERR_MPI_NEGATIVE_VALUE          -0x000A  /* The input arguments are negative or result in illegal output. */
+#define ESP32C3_ERR_MPI_DIVISION_BY_ZERO        -0x000C  /* The input argument for division is zero, which is not allowed. */
+#define ESP32C3_ERR_MPI_NOT_ACCEPTABLE          -0x000E  /* The input arguments are not acceptable. */
+#define ESP32C3_ERR_MPI_ALLOC_FAILED            -0x0010  /* Memory allocation failed. */
 
 #define ESP32C3_MPI_CHK(f, a)               \
   do                                        \
@@ -72,7 +72,7 @@ extern "C"
 /* Maximum size of MPIs allowed in bits and bytes for user-MPIs. */
 #define ESP32C3_MPI_MAX_SIZE                1024
 
-/**< Maximum number of bits for usable MPIs. */
+/* Maximum number of bits for usable MPIs. */
 #define ESP32C3_MPI_MAX_BITS                (8 * ESP32C3_MPI_MAX_SIZE)
 
 /****************************************************************************

@@ -46,37 +46,37 @@ extern "C"
 
 typedef enum
 {
-    EFUSE_BLK0                 = 0,   /**< Number of eFuse BLOCK0. REPEAT_DATA */
+    EFUSE_BLK0                 = 0,   /* Number of eFuse BLOCK0. REPEAT_DATA */
 
-    EFUSE_BLK1                 = 1,   /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
+    EFUSE_BLK1                 = 1,   /* Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
 
-    EFUSE_BLK2                 = 2,   /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
-    EFUSE_BLK_SYS_DATA_PART1   = 2,   /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
+    EFUSE_BLK2                 = 2,   /* Number of eFuse BLOCK2. SYS_DATA_PART1 */
+    EFUSE_BLK_SYS_DATA_PART1   = 2,   /* Number of eFuse BLOCK2. SYS_DATA_PART1 */
 
-    EFUSE_BLK3                 = 3,   /**< Number of eFuse BLOCK3. USER_DATA */
-    EFUSE_BLK_USER_DATA        = 3,   /**< Number of eFuse BLOCK3. USER_DATA */
+    EFUSE_BLK3                 = 3,   /* Number of eFuse BLOCK3. USER_DATA */
+    EFUSE_BLK_USER_DATA        = 3,   /* Number of eFuse BLOCK3. USER_DATA */
 
-    EFUSE_BLK4                 = 4,   /**< Number of eFuse BLOCK4. KEY0 */
-    EFUSE_BLK_KEY0             = 4,   /**< Number of eFuse BLOCK4. KEY0 */
+    EFUSE_BLK4                 = 4,   /* Number of eFuse BLOCK4. KEY0 */
+    EFUSE_BLK_KEY0             = 4,   /* Number of eFuse BLOCK4. KEY0 */
 
-    EFUSE_BLK5                 = 5,   /**< Number of eFuse BLOCK5. KEY1 */
-    EFUSE_BLK_KEY1             = 5,   /**< Number of eFuse BLOCK5. KEY1 */
+    EFUSE_BLK5                 = 5,   /* Number of eFuse BLOCK5. KEY1 */
+    EFUSE_BLK_KEY1             = 5,   /* Number of eFuse BLOCK5. KEY1 */
 
-    EFUSE_BLK6                 = 6,   /**< Number of eFuse BLOCK6. KEY2 */
-    EFUSE_BLK_KEY2             = 6,   /**< Number of eFuse BLOCK6. KEY2 */
+    EFUSE_BLK6                 = 6,   /* Number of eFuse BLOCK6. KEY2 */
+    EFUSE_BLK_KEY2             = 6,   /* Number of eFuse BLOCK6. KEY2 */
 
-    EFUSE_BLK7                 = 7,   /**< Number of eFuse BLOCK7. KEY3 */
-    EFUSE_BLK_KEY3             = 7,   /**< Number of eFuse BLOCK7. KEY3 */
+    EFUSE_BLK7                 = 7,   /* Number of eFuse BLOCK7. KEY3 */
+    EFUSE_BLK_KEY3             = 7,   /* Number of eFuse BLOCK7. KEY3 */
 
-    EFUSE_BLK8                 = 8,   /**< Number of eFuse BLOCK8. KEY4 */
-    EFUSE_BLK_KEY4             = 8,   /**< Number of eFuse BLOCK8. KEY4 */
+    EFUSE_BLK8                 = 8,   /* Number of eFuse BLOCK8. KEY4 */
+    EFUSE_BLK_KEY4             = 8,   /* Number of eFuse BLOCK8. KEY4 */
 
-    EFUSE_BLK9                 = 9,   /**< Number of eFuse BLOCK9. KEY5 */
-    EFUSE_BLK_KEY5             = 9,   /**< Number of eFuse BLOCK9. KEY5 */
+    EFUSE_BLK9                 = 9,   /* Number of eFuse BLOCK9. KEY5 */
+    EFUSE_BLK_KEY5             = 9,   /* Number of eFuse BLOCK9. KEY5 */
     EFUSE_BLK_KEY_MAX          = 10,
 
-    EFUSE_BLK10                = 10,  /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
-    EFUSE_BLK_SYS_DATA_PART2   = 10,  /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
+    EFUSE_BLK10                = 10,  /* Number of eFuse BLOCK10. SYS_DATA_PART2 */
+    EFUSE_BLK_SYS_DATA_PART2   = 10,  /* Number of eFuse BLOCK10. SYS_DATA_PART2 */
 
     EFUSE_BLK_MAX
 } esp_efuse_block_t;

@@ -46,28 +46,28 @@ extern "C"
 
 /* RSA Error codes */
 
-#define ESP32C3_ERR_RSA_BAD_INPUT_DATA                    -0x4080  /**< Bad input parameters to function. */
-#define ESP32C3_ERR_RSA_INVALID_PADDING                   -0x4100  /**< Input data contains invalid padding and is rejected. */
-#define ESP32C3_ERR_RSA_KEY_GEN_FAILED                    -0x4180  /**< Something failed during generation of a key. */
-#define ESP32C3_ERR_RSA_KEY_CHECK_FAILED                  -0x4200  /**< Key failed to pass the validity check of the library. */
-#define ESP32C3_ERR_RSA_PUBLIC_FAILED                     -0x4280  /**< The public key operation failed. */
-#define ESP32C3_ERR_RSA_PRIVATE_FAILED                    -0x4300  /**< The private key operation failed. */
-#define ESP32C3_ERR_RSA_VERIFY_FAILED                     -0x4380  /**< The PKCS#1 verification failed. */
-#define ESP32C3_ERR_RSA_OUTPUT_TOO_LARGE                  -0x4400  /**< The output buffer for decryption is not large enough. */
-#define ESP32C3_ERR_RSA_RNG_FAILED                        -0x4480  /**< The random generator failed to generate non-zeros. */
+#define ESP32C3_ERR_RSA_BAD_INPUT_DATA                    -0x4080  /* Bad input parameters to function. */
+#define ESP32C3_ERR_RSA_INVALID_PADDING                   -0x4100  /* Input data contains invalid padding and is rejected. */
+#define ESP32C3_ERR_RSA_KEY_GEN_FAILED                    -0x4180  /* Something failed during generation of a key. */
+#define ESP32C3_ERR_RSA_KEY_CHECK_FAILED                  -0x4200  /* Key failed to pass the validity check of the library. */
+#define ESP32C3_ERR_RSA_PUBLIC_FAILED                     -0x4280  /* The public key operation failed. */
+#define ESP32C3_ERR_RSA_PRIVATE_FAILED                    -0x4300  /* The private key operation failed. */
+#define ESP32C3_ERR_RSA_VERIFY_FAILED                     -0x4380  /* The PKCS#1 verification failed. */
+#define ESP32C3_ERR_RSA_OUTPUT_TOO_LARGE                  -0x4400  /* The output buffer for decryption is not large enough. */
+#define ESP32C3_ERR_RSA_RNG_FAILED                        -0x4480  /* The random generator failed to generate non-zeros. */
 
 /* RSA constants */
 
-#define ESP32C3_RSA_PUBLIC      0 /**< Request private key operation. */
-#define ESP32C3_RSA_PRIVATE     1 /**< Request public key operation. */
+#define ESP32C3_RSA_PUBLIC          0 /* Request private key operation. */
+#define ESP32C3_RSA_PRIVATE         1 /* Request public key operation. */
 
-#define ESP32C3_RSA_PKCS_V15    0 /**< Use PKCS#1 v1.5 encoding. */
-#define ESP32C3_RSA_PKCS_V21    1 /**< Use PKCS#1 v2.1 encoding. */
+#define ESP32C3_RSA_PKCS_V15        0 /* Use PKCS#1 v1.5 encoding. */
+#define ESP32C3_RSA_PKCS_V21        1 /* Use PKCS#1 v2.1 encoding. */
 
-#define ESP32C3_RSA_SIGN        1 /**< Identifier for RSA signature operations. */
-#define ESP32C3_RSA_CRYPT       2 /**< Identifier for RSA encryption and decryption operations. */
+#define ESP32C3_RSA_SIGN            1 /* Identifier for RSA signature operations. */
+#define ESP32C3_RSA_CRYPT           2 /* Identifier for RSA encryption and decryption operations. */
 
-#define ESP32C3_RSA_SALT_LEN_ANY    -1
+#define ESP32C3_RSA_SALT_LEN_ANY   -1
 
 /****************************************************************************
  * Public Types
@@ -79,8 +79,8 @@ extern "C"
 
 struct esp32c3_rsa_context_s
 {
-    int ver;                    /* Always 0 */
-    size_t len;                 /* The size of \p N in Bytes */
+    int ver;                             /* Always 0 */
+    size_t len;                          /* The size of \p N in Bytes */
 
     struct esp32c3_mpi_s N;              /* The public modulus */
     struct esp32c3_mpi_s E;              /* The public exponent */
@@ -101,8 +101,8 @@ struct esp32c3_rsa_context_s
     struct esp32c3_mpi_s VI;             /* The cached blinding value */
     struct esp32c3_mpi_s VF;             /* The cached un-blinding value */
 
-    int padding;                /* Selects padding mode */
-    int hash_id;                /* Hash identifier */
+    int padding;                         /* Selects padding mode */
+    int hash_id;                         /* Hash identifier */
 };
 
 /****************************************************************************