HDL (Verilog ) generation using TVM flow

[satml]

I am trying to generate Verilog RTL from trained DNN models ( either pytorch or tensorflow ). Is that possible usig TVM flow ? if yes and if any of you have done similar work, can you please point me to documentation or examples ?

[comaniac]

This repo is used to maintain RFCs for proposing changes and features.
Please raise the questions in discuss forum: https://discuss.tvm.apache.org/