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This new RFC explores how TVM can be utilized to generate code for the SME ISA to achieve improved inference performance on supported Arm®-based hardware implementing the SME extension.
The text was updated successfully, but these errors were encountered:
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Apr 21, 2024
Introduction
The TVM community has worked since the v0.15.0 release to deliver the following new exciting improvements! This release version is:
The main tags are below (bold text is with lots of progress):
Please visit the full listing of commits for a complete view: v0.16.dev0...v0.16.0.rc0.
Community
RFCs
This new RFC explores how TVM can be utilized to generate code for the SME ISA to achieve improved inference performance on supported Arm®-based hardware implementing the SME extension.
Arith
BYOC
BugFix
CI
Docker
Disco
Session.import_python_module
methodDlight
Docs
tvm.ir.make_node
DataflowBlock
s and encourage usingConvertToDataflow
extern.py
for SphinxFrontend
Hexagon
dma_wait
builtinLLVM
MetaSchedule
opt_level
oftune_relay()
adjustableMetal
OpenCL & CLML
ROCm
tanh
,erf
,log
Relax
transform.LazyGetInput
tanh
,exp
,negative
, andpermute
let var = R.const
bindingscall_tir_inplace
inFuseTIR
andFuseOps
reconstruct_from_cache
kernel and add testRelay
Runtime
TIR
BindTarget
to specify target for FP8 legalizationTOPI
arm_cpu
targetsTVMC
TVMScript
call_packed
semantics to support empty sinfo_argsVulkan
cuda & cutlass & tensorrt
micoNPU
web
kv_state
andrnn_state
to wasm_runtimeMisc
The text was updated successfully, but these errors were encountered: