Add missing Slice layout fallback check of stride=1.

[lazycal]

When doing layout optimization for slice, if start or end are divisibly by the pack factor and stride=1, a layout_transform can be saved. However, previous code only checks stride=1 when axes is not specified, as in

tvm/src/relay/op/tensor/transform.cc

Lines 2735 to 2741 in 2fc7d16

	if (strides.defined() && i < strides.size()) {
	auto stride = strides[i];
	// arbitrary stride is not supported
	if (stride.defined() && stride->value != 1) {
	return out_default;
	}
	}

. This PR adds the same check to the other branch.

The following model can trigger this bug with error message ...In particular `Tensor[(4, 1, 1, 1), float32]` does not match `Tensor[(4, 3, 1, 1), float32]` .

import tvm
from tvm import relay
import numpy as np
from tvm.relay import testing

x = relay.var("data", shape=(4, 12, 1, 1), dtype="float32")
O, I, H, W = 9, 12, 1, 1
conv_out = relay.nn.conv2d(
    x,
    relay.const(np.ones([O, I, H, W], dtype="float32")),
    strides=[1, 1],
    padding=0,
    channels=O,
    kernel_size=[H, W],
)
bias_out = relay.nn.bias_add(
    conv_out, relay.const(np.ones([O], dtype="float32")))
y = relay.strided_slice(bias_out, begin=[3], end=[6], strides=[3], axes=[1])

mod, _ = testing.create_workload(y)
with tvm.transform.PassContext(opt_level=3):
    with tvm.target.Target("llvm"):
        mod = relay.transform.CanonicalizeOps()(mod)
        mod = relay.transform.AlterOpLayout()(mod)

cc @masahi

[masahi]

The CI is having an flaky issue with i386, please wait until #10687 lands (or run more jobs until it succeeds)

[lazycal]

Not sure what is going on with the CI. I thought my previous commit was stuck at some stage but now I saw a check there, but still I saw tvm-ci/pr-merge Expected — Waiting for status to be reported as one pending check. Could you take a look @masahi ?