[HEXAGON][TOPI] This PR adjusts schedules so >64 length vector loads/…#12471
Merged
masahi merged 1 commit intoapache:mainfrom Aug 18, 2022
Merged
[HEXAGON][TOPI] This PR adjusts schedules so >64 length vector loads/…#12471masahi merged 1 commit intoapache:mainfrom
masahi merged 1 commit intoapache:mainfrom
Conversation
…stores are not generated at LLVM level. This is a workaround for an instruction selection issue in current version of llvm for hexagon
Contributor
Author
Contributor
Author
|
@tvm-bot rerun |
masahi
approved these changes
Aug 18, 2022
xinetzone
pushed a commit
to daobook/tvm
that referenced
this pull request
Nov 25, 2022
…stores are not generated at LLVM level. This is a workaround for an instruction selection issue in current version of llvm for hexagon (apache#12471)
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
…stores are not generated at LLVM level. This is a workaround for an instruction selection issue in current version of llvm for hexagon
Thanks for contributing to TVM! Please refer to guideline https://tvm.apache.org/docs/contribute/ for useful information and tips. After the pull request is submitted, please request code reviews from Reviewers by @ them in the pull request thread.
cc @mehrdadh