Add full technical wiki: every timing parameter explained in depth 12 pages covering primary timings (CL/tRCD/tRP/tRAS/tRC), refresh (tRFC), bank-group/activation timings (tFAW/tRRD/tCCD), write/turnaround timings (tWR/tWTR/tRTP), inferred values (tCWL/command rate), voltage, SPD byte structure and timebase encoding, module organization and the capacity formula, module-type/ECC compatibility, XMP profiles, the worst-case computation methodology (including the real tRC bug this project found and fixed), and a design-decisions FAQ.

apoage committed Jul 20, 2026