Embedded firmware and FPGA design engineer. I build things on real hardware — not just simulation.
RV32IM Pipelined CPU + Systolic Array Coprocessor — View Repo 5-stage pipelined RISC-V processor with a custom 4×4 INT8 systolic array coprocessor in SystemVerilog. Validated on real Zynq UltraScale+ silicon — 138 MHz, 4,777 LUTs, 36/36 tests, correct output on board LEDs.
STM32 Multi-Sensor DAQ — Repo coming soon Register-level I2C/SPI drivers on STM32F446RE, CAN bus via SN65HVD230, FreeRTOS with 4 concurrent tasks. No libraries. Datasheets and registers.
Firmware: C (bare-metal) · FreeRTOS · STM32 · ARM Cortex-M · ESP32 · 8051 HDL & FPGA: SystemVerilog · Verilog · Xilinx Vivado · Zynq UltraScale+ Protocols: I2C · SPI · UART · CAN · AXI4-Lite · MQTT Debug: Oscilloscopes · Logic Analyzers · Soldering
Seeking Fall 2026 co-op → Hardware · Embedded · FPGA · Firmware