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| 1 | +/* |
| 2 | + * Base device tree for BeagleBone Green with CTAG face2|4 Audio Card |
| 3 | + * |
| 4 | + * Author: Henrik Langer <henni19790@googlemail.com> |
| 5 | + * based on |
| 6 | + BeagleBone Black and BeagleBone Green device tree |
| 7 | + * |
| 8 | + * This program is free software; you can redistribute it and/or modify |
| 9 | + * it under the terms of the GNU General Public License version 2 as |
| 10 | + * published by the Free Software Foundation. |
| 11 | + */ |
| 12 | +/dts-v1/; |
| 13 | + |
| 14 | +#include "am33xx.dtsi" |
| 15 | +#include "am335x-bone-common.dtsi" |
| 16 | +//#include "am33xx-overlay-edma-fix.dtsi" // leads to problems with SPI |
| 17 | + |
| 18 | +/ { |
| 19 | + model = "TI AM335x BeagleBone Green AudioCard"; |
| 20 | + compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; |
| 21 | + |
| 22 | + /* |
| 23 | + Optional SW SPI interface |
| 24 | + (see BB-CTAG-SW-8CH-00A0.dts for more details) |
| 25 | + */ |
| 26 | + spi_gpio: spi_gpio { |
| 27 | + compatible = "spi-gpio"; |
| 28 | + #address-cells = <1>; |
| 29 | + #size-cells = <0>; |
| 30 | + |
| 31 | + gpio-sck = <&gpio2 24 0>; |
| 32 | + gpio-mosi = <&gpio2 25 0>; |
| 33 | + gpio-miso = <&gpio2 23 0>; |
| 34 | + cs-gpios = <&gpio2 22 0 &gpio1 29 0>; |
| 35 | + num-chipselects = <2>; |
| 36 | + |
| 37 | + status = "disabled"; |
| 38 | + }; |
| 39 | +}; |
| 40 | + |
| 41 | +&ldo3_reg { |
| 42 | + regulator-min-microvolt = <1800000>; |
| 43 | + regulator-max-microvolt = <1800000>; |
| 44 | + regulator-always-on; |
| 45 | +}; |
| 46 | + |
| 47 | +&mmc1 { |
| 48 | + vmmc-supply = <&vmmcsd_fixed>; |
| 49 | +}; |
| 50 | + |
| 51 | +&mmc2 { |
| 52 | + vmmc-supply = <&vmmcsd_fixed>; |
| 53 | + pinctrl-names = "default"; |
| 54 | + pinctrl-0 = <&emmc_pins>; |
| 55 | + bus-width = <8>; |
| 56 | + status = "okay"; |
| 57 | +}; |
| 58 | + |
| 59 | +&cpu0_opp_table { |
| 60 | + /* |
| 61 | + * All PG 2.0 silicon may not support 1GHz but some of the early |
| 62 | + * BeagleBone Blacks have PG 2.0 silicon which is guaranteed |
| 63 | + * to support 1GHz OPP so enable it for PG 2.0 on this board. |
| 64 | + */ |
| 65 | + oppnitro@1000000000 { |
| 66 | + opp-supported-hw = <0x06 0x0100>; |
| 67 | + }; |
| 68 | +}; |
| 69 | + |
| 70 | +&am33xx_pinmux { |
| 71 | + mcasp0_pins: mcasp0_pins { |
| 72 | + pinctrl-single,pins = < |
| 73 | + 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx */ |
| 74 | + 0x19c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_axr2 */ |
| 75 | + 0x194 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx */ |
| 76 | + 0x190 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx */ |
| 77 | + 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsr */ |
| 78 | + 0x078 (PIN_INPUT_PULLDOWN | MUX_MODE6) /* mcasp0_aclkr */ |
| 79 | + 0x198 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0 */ |
| 80 | + 0x06c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpio1[27] (enable oscillator) */ |
| 81 | + >; |
| 82 | + }; |
| 83 | + |
| 84 | + mcasp0_pins_sleep: mcasp0_pins_sleep { |
| 85 | + pinctrl-single,pins = < |
| 86 | + 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx */ |
| 87 | + 0x19c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_axr2 */ |
| 88 | + 0x194 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_fsx */ |
| 89 | + 0x190 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_aclkx */ |
| 90 | + 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsr */ |
| 91 | + 0x078 (PIN_INPUT_PULLDOWN | MUX_MODE6) /* mcasp0_aclkr */ |
| 92 | + 0x198 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_axr0 */ |
| 93 | + 0x06c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpio1[27] */ |
| 94 | + >; |
| 95 | + }; |
| 96 | +}; |
| 97 | + |
| 98 | +&mcasp0 { |
| 99 | + pinctrl-names = "default", "sleep"; |
| 100 | + pinctrl-0 = <&mcasp0_pins>; |
| 101 | + pinctrl-1 = <&mcasp0_pins_sleep>; |
| 102 | + status = "okay"; |
| 103 | + op-mode = <0>; /* MCASP_IIS_MODE */ |
| 104 | + tdm-slots = <2>; |
| 105 | + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ |
| 106 | + 2 0 1 0 |
| 107 | + >; |
| 108 | + tx-num-evt = <1>; |
| 109 | + rx-num-evt = <1>; |
| 110 | +}; |
| 111 | + |
| 112 | +/ { |
| 113 | + clk_mcasp0_fixed: clk_mcasp0_fixed { |
| 114 | + #clock-cells = <0>; |
| 115 | + compatible = "fixed-clock"; |
| 116 | + clock-frequency = <24576000>; |
| 117 | + }; |
| 118 | + |
| 119 | + clk_mcasp0: clk_mcasp0 { |
| 120 | + #clock-cells = <0>; |
| 121 | + compatible = "gpio-gate-clock"; |
| 122 | + clocks = <&clk_mcasp0_fixed>; |
| 123 | + enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ |
| 124 | + }; |
| 125 | +}; |
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