The design (attached) is converted from Verilog to Blif (by Yosys).
It is a 2-bit register that can only be updated to 3 or 0, based on other signals. It looks like this:
always @(posedge clk) begin
if (rst) begin
reg_mstatus_mpp <= rst_mstatus_mpp;
end else begin
if (wen) begin
if (T_5098) begin
if (T_6142) begin
reg_mstatus_mpp <= 2'h3;
end else begin
reg_mstatus_mpp <= 2'h0;
end
end else begin
if (insn_ret) begin
if (T_5454) begin
reg_mstatus_mpp <= 2'h0;
...
And the property to prove is this register should not be 1 (2'b01)
When the initial value is 00:
abc 01> read_blif wrapper_init00.blif
abc 02> strash
abc 03> pdr
Invariant F[2] : 1 clauses with 2 flops (out of 10) (cex = 0, ave = 2.00)
Verification of invariant with 1 clauses was successful. Time = 0.00 sec
Property proved. Time = 0.01 sec
abc 03> inv_print
Invariant contains 1 clauses with 2 literals and 2 flops (out of 10).
abc 03> inv_print -v
Invariant contains 1 clauses with 2 literals and 2 flops (out of 10).
10 1
abc 03> ***EOF***
This is as expected.
When initial value is 11:
UC Berkeley, ABC 1.01 (compiled Apr 30 2019 02:29:30)
abc 01> read_blif wrapper_init11.blif
abc 02> strash
abc 03> pdr
Invariant F[1] : 1 clauses with 2 flops (out of 10) (cex = 0, ave = 2.00)
Verification of invariant with 1 clauses was successful. Time = 0.00 sec
Property proved. Time = 0.01 sec
abc 03> inv_print -v
Invariant contains 1 clauses with 2 literals and 2 flops (out of 10).
01 1
This can be interpreted as reg_mstatus_mpp != 2'b10 , which does not imply reg_mstatus_mpp != 2'b01
test.zip
The design (attached) is converted from Verilog to Blif (by Yosys).
It is a 2-bit register that can only be updated to 3 or 0, based on other signals. It looks like this:
And the property to prove is this register should not be 1 (2'b01)
When the initial value is 00:
This is as expected.
When initial value is 11:
This can be interpreted as
reg_mstatus_mpp != 2'b10, which does not implyreg_mstatus_mpp != 2'b01test.zip