Learn Verilog and SystemVerilog from Scratch

The purpose of designing this project is to teach the Verilog (and SystemVerilog) languages. Prerequisites are generally not required for learning the Verilog language, and basic principles such as the concepts of logic circuits and digital systems are explained. Knowledge about the logic circuits can be useful for better understanding and more practice.

References

[1].Sutherland, Stuart, RTL modeling with SystemVerilog for simulation and synthesis: using SystemVerilog for ASIC and FPGA design, Sutherland HDL, 2018.

[2]. Sutherland, Stuart, Simon Davidmann, and Peter Flake, SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling, Springer Science & Business Media, 2006.