fix SWD turnaround issues#1711
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Target is a GD32F303 on a Keyboardio Model 100 keyboard. Probe is BMP native, hardware v2.3b. There are 10k pull up resistors on all JTAG/SWD lines, except JTCLK/SWDCLK, which has a 10k pull down. (I misread the schematic when reporting this to Discord earlier.) In any case, the user manual for the chip says at reset, JTDI, JTMS/SWDIO, NJTRST are pulled up, JTCK/SWDCLK is pulled down, and JTDO is floating. |
dragonmux
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This is looking good - there are a couple of stylistic review notes we've got, but functionally this all looks good - we'll get this merged once the review items have been addressed as we can see it fixes the bug and we're satisfied that it's all functioning properly.
Particularly appreciate this gives an explanation for the attach bug we'd hit near the release of v1.9 and couldn't explain! We knew at the time that protocol recovery was just papering over the real problem, but this explains exactly what the problem actually was and fixes its root cause which is awesome.
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Thanks for the review! I addressed your style comments. |
dragonmux
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All looks good to us now - good stuff, merging once we've briefly tested this with a couple of targets for good measure. Thank you for the contribution!
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I created the patch for the missing turnaround delay before seeing that @stansotn had already made a very similar one. I can add credit to the commit message, if that's desired. |
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Yeah, probably a kindness to add a |
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Well, we can confirm this all works as intended on our RP2040 and a STM32F411 and the attach protocol recovery trigger is now gone 👍🏼 |
I just changed the authorship of the commit to my personal email (gmail). I consent to be included as co-author. Thanks for asking! |
Fix two problems with SWD turnaround: * When going from output to input, add a missing delay loop, so the clock low period is consistent. This prevents problems with a missed clock edge when the clock speed is intentionally slowed to accommodate lower bandwidth connections to the target. * Always set the clock low at the end of a turnaround. Otherwise, when floating the clock after a read transaction, the most recent clock state was driven high. If there's a pull down on the clock, a subsequent clock reactivation would drive the clock high, producing an extra rising clock edge. This sometimes causes (recoverable) protocol error states when re-attaching after a detach. Co-Authored-By: Stanislav Sotnikov <stanislav.sotnikov145@gmail.com>
Add missing idle cycles after SWD read transactions. ADIv5 (ARM IHI0031G) §B4.1.1 requires at least 8 idle cycles after any SWD transaction (not just write transactions) before stopping the clock. This does add some delays to read transactions where there were previously none. A future change could conditionally disable the idle cycles for both read and write transactions if it is known that a new transaction will immediately follow.
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Merging now the authorship bit is solved, thank you all for your efforts and work on this! |
Detailed description
There were multiple problems with SWD turnaround. In the write-to-read direction, a short clock pulse could be produced (#1706). When terminating a read transaction, the clock wasn't driven low. If a subsequent clock float was requested, as for a detach, the clock would float low, then be driven high when re-enabled, causing an extra rising clock edge.
Additionally, idle cycles weren't being inserted as required after a read transaction.
There's a small chance of a regression with targets that pull the SWD clock high.
Your checklist for this pull request
make PROBE_HOST=native)make PROBE_HOST=hosted)Closing issues
Fixes #1706.
Details
These are debug logs from BMDA.
Log excerpt from unpatched, attaching after detaching. Note the non-response error after re-enabling the clock.
Full log from unpatched code:
unpatched.txt
Log excerpt from patched, with only the
swdptap_turnaroundfix. Note the lack of non-response error after re-enabling the clock.Full log from patch with only
swdptap_turnaroundfix:ta-no-8idle.txt
Full log with both commits:
ta-with-8idle.txt