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This commit fixes another issue we've discovered in the wasip3 prototyping repository about a code pattern in wasm which Miri flags as un-sound. Specifically what happened was: * Invocation of WebAssembly went through `VMFuncRef::array_call` which takes a `&self` parameter. * Inside of WebAssembly though a `ref.func` instruction, or anything else that references the original exported function, will re-initialize the `VMFuncRef` which writes the `&self` up the stack, which is not sound. Fixing this required changing the signature of `array_call` from `&self` to `me: NonNull<VMFuncRef>`, and the signature was already `unsafe` so this is a new unsafe contract for that signature. In fixing this, however, it was discovered that a mistake was made in #10943 where some internal functions for re-initializing a `VMFuncRef` relied on the previous signature of `&mut self` but that PR switche to `&self`. This PR corrects these signatures to `Pin<&mut Self>` and then plumbs around the necessary changes, notably causing some refactoring in component-related bits.
This commit fixes another Miri issue flagged in wasip3-prototyping as more modules are run through Miri. Specifically table elements are now read/written with `VmPtr<T>` to ensure the provenance of their at-rest value is handled correctly.
With the introduction of the scratch register scope, it's safer to acquire and work with such registers, however it's crucial to delay the acquisition of such registers as close as possible to emission time, to avoid introducing conflicts with other operations that might also require them. This commit defers the acquisition of the scratch registers until after the temporary register for the convert operation has been allocated, fixing potential conflicts in case of a spill.
This commit fixes a typo mistake from #10588 where the option specified there was actually invalid. This error got covered up by accident when generating the fuzz test case, however, meaning that the error was not noticed. This changes builder configuration to using `.unwrap()` more liberally for options that are all known should be enabled.
* wasi-nn: update OpenVINO to v2025.1 This updates the version of the bindings used for communicating with OpenVINO to v0.9.0 as well as the GitHub action used to install the latest version of OpenVINO (v2025.1.0) in CI. * deny: remove skipped `wit-bindgen` This avoids an `unmatched-skip-root` warning emitted by `cargo-deny`: "skip tree root was not found in the dependency graph." * deny: ignore `file-per-thread-logger` This crate has not been updated in a while and thus imports some older dependencies, causing duplicates that `cargo-deny` flags. * vet: certify update of `openvino-*` crates prtest:full
* c-api: component-model: Resource table, WASI * WASIP2 context builder * Add include * Rename function * Add a simple test * Add comments prtest:full
Using the trait through `std` at this point is just vestigal. Closes #11059
This can all happen automatically in the interpreter, so no need to otherwise record these traps unnecessarily.
* Initial component model and GC support in fused adapters This lays down the initial infrastructure for support for GC in our fused adapters for the component model. We keep track of whether each lifted/lowered function wants args/results as GC values or in linear memory. We additionally plumb through the core function types of the functions being lifted and lowered for (eventual) use with GC adapters. Ultimately, this commit is enough to fuse together lifted and lowered functions where one or both are using the GC variant of the canonical ABI. Attempting to actually pass arguments will hit `todo!()`s. The work of implementing those `todo!()`s is left to future commits. * Address review feedback * More review feedback * Fix wasmtime-fuzzing build * Fix the `factc` example program * cargo fmt * Fix fact-valid-module fuzzer
Signed-off-by: Roman Volosatovs <rvolosatovs@riseup.net>
…he meta crate (#11065)
* Cranelift: Generate integer numeric ops and conversions for ISLE in the meta crate
This automatically generates operations and conversions for integer types for
use in ISLE.
Supported types are: `{i,u}{8,16,32,64,128}`
We generate
* Comparisons (eq, ne, lt, lt_eq, gt, gt_eq)
* Arithmetic operations (add, sub, mul, div, neg)
* These each have checked, wrapping, and unwrapping variants
* Bitwise operations (and, or, xor, shifts, counting leading/trailing zeros/ones)
* A variety of predicates (is_zero, is_power_of_two, is_odd, etc...)
* These generate both partial constructors and a handful of extractors
* Conversions
* These come in a variety of flavors: fallible, infallible, truncating,
unwrapping, sign-reinterpretation
* Fallible conversions are also available as an extractor
* Fix copy paste
* Rename `x_reinterpret_as_y` to `x_cast_[un]signed`
* Collapse some fallible conversions in pulley lowering
* Clean up pulley iconst lowering, make sure narrowest `xconst*` instruction is always used
* Avoid an unnecessary truncation in riscv64 lowering
* Use extractor instead of partial constructor in x64 `imm` rule
* Clean up `op mem, imm` x64 lowering rules
* Use `(i64_eq a b)` instead of `(u64_eq (i64_cast_unsigned a) (i64_cast_unsigned b))`
* Rename `<ty>_unwrapping_<op>` to `<ty>_<op>`
* x64: Migrate cmp/test to the new assembler This commit migrates the `cmp` and `test` family of instructions, the `CmpRmiR` variant in ISLE, to the new assembler. This required fiddling with various helpers for immediates and such throughout a few locations and refactoring various callsites of creating these instructions to fit nicely into these new idioms. EFLAGS-writing instructions with no other results are now also modeled in the assembler as `ProducesFlags` rather than `SideEffectNoResult` as their base case enabling using the generated constructors a bit more too. No functional change is expected from this, it should just be internal refactoring. * Swap between rm and mr encodings
The differential fuzzer found an incosistency between Wasmtime/Wasmi, related to the `wide_arithmetic` proposal. I've reported the issue upstream (wasmi-labs/wasmi#1544)
The gdb version in Ubuntu 24.04 fails on our synthetic DWARF because: 1. the synthetic DWARF unit has no DW_AT_language 2. synthetic types are referenced from a unit that does have DW_AT_language 3. this triggers https://sourceware.org/bugzilla/show_bug.cgi?id=32431 Workaround this issue by specifying DW_LANG_C11. This may not be exactly the right meaning, but it should be safe.
…#11080) * Add pack convert (*packss*, *packus*) instructions to new assembler * Use the or_avx ISLE rule for pack convert instructions
There are custom encodings of shift/rotate instructions when the amount being shifted/rotated by is 1, and these encodings are slightly smaller than the default encodings. This commit updates instruction selection to use these encodings when shifts-by-immediate are encountered. Note that these new instructions in the assembler all have custom `Display` implementations. The Capstone disassembly is a bit odd where the immediate is printed as `$1` instead of `$0x1` and additionally the immediate isn't printed at all when the thing-to-be-shifted is a memory location.
* Improve debug formatting for primary/secondary map * clippy suggestion * review suggestions
wasm-opt will strip DWARF debug info, which causes a test failure for debug::lldb::dwarf_codegen_optimized_wasm_optimized. clang automatically runs wasm-opt if it is found in PATH and if optimization is enabled. clang-20 has a --no-wasm-opt option, but that doesn't work for wasi-sdk-25.
and trivial to trust because published by wasmtime-publish
* asm: cover more of SSE in `Features::is_sse()` * asm: add `VexPrefix::two_op` This is simply a convenience method when `vvvv` is unspecified. * asm: print failing instruction in SSE-to-AVX alternate mapping * asm: fill out AVX functionality for unary VEX instructions These include `vmov*`, `vpmov*`, `vsqrt`, and some lane operations. * asm: add `Location::xmm_m8` * asm: add av2 feature * asm: add AVX broadcast instructions * x64: add `is_mem` for extracting addresses from `XmmMem` * x64: convert unary VEX instructions * x64: bless Cranelift filetests * x64: use alternate AVX version for `pabs*` * x64: bless `pabs*` Cranelift filetests * x64: remove `XmmUnaryRmRVex` and now-unnecessary `AvxOpcode`s * winch: convert `XmmUnaryRmRVex` instructions
…asmtime::Config` (#11087) Fixes https://oss-fuzz.com/testcase-detail/6524398096154624
* `Lower::lower` becomes `Lower::linear_lower_to_flat` * `Lower::store` becomes `Lower::linear_lower_to_memory` * `Lift::lift` becomes `Lift::linear_lift_from_flat` * `Lift::load` becomes `Lift::linear_lift_from_memory` This renaming is to distinguish these linear-memory methods from the GC versions that will be added in follow up commits. No functional changes here, just renaming.
* Make auto-publish script more robust * Add a helper to run `curl` and get the output * Print an error if `curl` fails to help diagnose what went wrong in the future * Pass a custom `--user-agent` which is requested by crates.io's [data access policy](https://crates.io/data-access). * Don't continue publishing if `curl` fails
* x64: Add a shrink-before-emit optimization This commit adds a helper function to attempt to shrink a function just before emission if possible based on the results of register allocation. While many instructions can be selected ahead of time (e.g. instructions with smaller immediate widths) some are only possible after register allocation has happened. For example the `AND RAX, imm32` instruction is never generated in ISLE because it doesn't make sense to constrain a register to only `RAX`, but if register allocation happened to put `AND r/m64, imm32` into `RAX` then it's possible to use the more compact encoding instead. This function updates the emission of external instructions to, just before emission, attempt to pattern-match these instructions and shrink to a smaller instruction. This is done for a number of instructions which support a smaller encoding when the operands are `RAX` and an immediate. In the future my thinking was to use this additionally for the optimization to change `LEA` instructions into `ADD` instructions if the src/destination are equal and the addressing mode matches. * x64: Migrate `lea` to the new assembler Adding `lea` is easy enough but preserving the optimization of using `add` instead of `lea` required a bit of finesse. This hooks into the `emit_maybe_shrink` added previously for implementing this. * Fix test build
This replaces all AVX versions of XMM lane extraction to use the new assembler. This removes the `Inst::XmmMovRMImmVex` and `Inst::XmmToGprImmVex` variants.
This commit adds all `cmov*` variants from the Intel manual to the new assembler. This then additionally removes the `Cmove` pseudo-inst in favor of these new instructions. One difference from before is that the naming in the `CC` enum does not exactly match what mnemonics Capstone uses to disassemble. For example `CC.NB` in ISLE corresponds to the Intel instruction `CMOVNB`. This instruction, however, has the same encoding as `CMOVAE` and Capstone disassembles as `CMOVAE`. This means that the instruction selection in ISLE isn't a 1:1 match with mnemonics. This additionally adds support in the assembler ISLE generation to understand that instructions which read EFLAGS generate a `ConsumesFlags` variant in their instruction helpers.
* wasi-nn: add feature to use custom ONNX Runtime * Change to onnx-download feature * Update onnx feature in CI, prtest:full
Signed-off-by: Joel Dice <joel.dice@fermyon.com>
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