Fix RISCV aliases

[slate5]

Your checklist for this pull request

• I've documented or updated the documentation of every API function and struct this PR changes.
• I've added tests that prove my fix is effective or that my feature works (if possible)

Detailed description

Fixing alias detection from issue #2861.

Test plan

$ cstool -dr riscv32 "0x67, 0x80, 0x50, 0x00"
 0  67 80 50 00  jr	5(ra)
	ID: 31 (jalr)
	Is alias: 1696 (jr) with REAL operand set
	op_count: 3
		operands[0].type: REG = zero
		operands[0].access: WRITE
		operands[1].type: REG = ra
		operands[1].access: READ
		operands[2].type: IMM = 0x5
		operands[2].access: READ

	Groups: jump 

$ cstool -d riscv64 "e780604c"
 0  e7 80 60 4c  jalr	0x4c6(ra)
	ID: 31 (jalr)
	Is alias: 1697 (jalr) with REAL operand set
	op_count: 2
		operands[0].type: REG = ra
		operands[0].access: READ
		operands[1].type: IMM = 0x4c6
		operands[1].access: READ

	Groups: jump 

$ cstool -d riscv32+corev 0x5BD5C540
 0  5b d5 c5 40  cv.mulhhu	a0, a1, a2
	ID: 395 (cv_mulhhun)
	Is alias: 1762 (cv.mulhhu) with REAL operand set
	op_count: 3
		operands[0].type: REG = a0
		operands[0].access: WRITE
		operands[1].type: REG = a1
		operands[1].access: READ
		operands[2].type: REG = a2
		operands[2].access: READ

	Groups: HasVendorXCVmac IsRV32 

Depends-on

The third example (cv.mulhhu) depends on capstone-engine/llvm-capstone#91.

Closing issues

closes #2861

[Rot127]

Please add the updated RISCVGenCSAliasMnemMap.inc and the test cases to tests/issues/issues.yaml

[Rot127]

cc @moste00

[Rot127]

Looks good! Thanks.
Please fix those tests and we are good to go when green.

[Rot127]

Suggested change

	is_alias: 0
	is_alias: -1