Aarch64/ARM64: Fix register access for LSE atomics#2978
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The LSE atomics (CAS, CASP, SWP and the LD<op>/ST<op> families) had empty operand access, so cs_regs_access reported neither the value registers read nor the destination written. Populate the access table, and handle the CASP register pairs in AArch64_reg_access, whose second element gets no access info from the printer.
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Detailed description
This is #2953 with the test case moved so it actually runs it.
Test plan
Added
Closing issues
closes #2953