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Issue with TAR auto incrementation #15
The ARM debug interface v5 doc states that TAR auto incrementalist is only guaranteed to work on the lower 10 bits of TAR. This is dealt with in code, by writing the TAR register every 1KB. However it assumes a 1KB alignment for address.
For example. On a cortex m0+ chip only the bottom 10 bits are supported. After that it appears to wrap back to the start of the 1KB region.
If we wrote 1KB to 0x200, The code would set TAR to 0x200, the first 512 bytes would be written as expected, then it would overflow / wrap / ... (this is implementation defined) and the second 512 bytes don't go where we expect them to go (on the cortex m0+ they get written to 0x000 - 0x1FF).
Instead the code should write up to the 1KB boundary and then change the TAR address.
I'm working on a patch for this now.