Implements matrix operations in SystemVerilog
Currently implemented matrix operations are: matrix transpose
Implemented with two barrel shifters and a number of RAMs equal to the number of columns in the matrix. The first matrix row is the first incoming data, and the first matrix column is the MSB of each incoming row. The size of the data (BIT_WIDTH) can be configured to any value as long as it fits evenly into ROW_WIDTH (the size in bits of each row) and satisfies the constraint NUM_ROWS*BIT_WIDTH = ROW_WIDTH.
Each column of the incoming matrix row is written into a different RAM. Initially, all writes will occur on vertical slices of the RAM, starting at address 0, 1, etc. Initially, the input data is shifted based on the number of rows that have been read previously. This is because if the input is not shifted at all, then the first row of the transposed matrix would all be placed into RAM #0. Barrel shifting the input causes the first row of the transposed matrix to be spread across all RAMs in a diagonal slice. This algorithm achieves 100% throughput by pingponging write and read addresses by first writing in vertical slices, then writing in diagonal slices while reading in diagonal slices, then writing in vertical slices while reading in vertical slices.
Once the final row of the matrix is written, then the transposed matrix will be read out row by row, MSB being the first column. If writes are not continuous, that is not an issue, there are two intermediate states that can be reached where only writing occurs on either diagonal or vertical stripes of the RAMs.