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@uenoku uenoku commented Jul 29, 2024

This fixes two bugs in #4286

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  • Bugfix

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@uenoku uenoku added the Bugfix Fixes a bug, will be included in release notes label Jul 29, 2024
@mwachs5
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mwachs5 commented Jul 29, 2024

is there a testcase we can add for this ?

@mwachs5 mwachs5 added this to the 7.0 milestone Jul 29, 2024
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uenoku commented Jul 30, 2024

is there a testcase we can add for this ?

I tried but it looks tricky to reproduce the error in chisel repo. Internally we use svsim in a slightly different way and it looks there is no issue if we used chisel3.simulator directly.

@jackkoenig jackkoenig merged commit da98687 into chipsalliance:main Jul 30, 2024
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I tried but it looks tricky to reproduce the error in chisel repo. Internally we use svsim in a slightly different way and it looks there is no issue if we used chisel3.simulator directly.

Our team do provide the VCS infrastructure for rocket-chip and T1. Do we need to adopt it for chisel?

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uenoku commented Jul 31, 2024

Our team do provide the VCS infrastructure for rocket-chip and T1. Do we need to adopt it for chisel?

No I don't think so. It was not backend specific and internally we use some wrapper for svsim that manually constructs ModuleInfo .

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4 participants