MBIST-256x4b

• The objective of this project is to develop a Memory Built-In Self-Test (MBIST) system for evaluating a 256 x 4-bit Static Random Access Memory (SRAM) cell. The testing approach utilizes checkerboard patterns along with uniform patterns of zeros and ones. The design of both the MBIST and the SRAM cell is synchronized to operate under the same clock frequency.

• For verification of the Register Transfer Level (RTL) design functionality, we employ HDL compiler tools alongside visualization technologies such as VCS (Verilog Compiled Simulator) and Verdi for an in-depth analysis and debug.

• The subsequent phase involves the synthesis and optimization of the design, executed using the Genus Synthesis Solution. This stage aims to refine the design for optimal performance and resource utilization, ensuring a reliable and efficient MBIST implementation for the SRAM cell."