FORGIX Board

Example designs and firmware for the Forgix board from Adiuvo Engineering — a Teensy 4.0 form-factor board combining an Efinix Trion T8 FPGA (T8F49I2X, 49-ball BGA) with a Raspberry Pi RP2350 microcontroller (RP2354A).

The RP2350 configures the Trion T8 over a passive SPI link and bridges USB to the host, while the FPGA fabric is broken out to the Teensy pin header.

• fpga_loader/ — host-side tooling for the Trion T8: the drag-and-drop reset/load helper reset_and_load.py (see Programming via drag-and-drop).
• rp2350_fw/ — RP2350 firmware: src/ (drag-and-drop MSC loader + CDC UART bridge, see Programming via drag-and-drop), built to forgix_t8_fw.uf2.

The pinout below was extracted from the KiCad schematic (RP2350_FPGA_eensy, American Embedded / Adiuvo).

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Architecture

flowchart LR
    USB([USB-C]) -->|USB_DP/DM| RP[RP2350<br/>RP2354A]
    VBUS([VIN / VBAT]) --> PSU[Power<br/>3V3 · 1V1]
    PSU --> RP
    PSU --> T8

    RP -->|SPI: CS/CLK/MOSI| T8[Trion T8<br/>T8F49I2X]
    RP -->|nRESET / OSC_EN| T8
    T8 -->|DONE / nSTATUS| RP

    RP -->|UART0/1| H
    T8 -->|GPIO 4-6, 9-23| H[[Teensy header<br/>pins 0..23]]
    T8 --> LED([RGB LED D1])
    SW([Button SW1]) --> T8

    classDef chip fill:#2b6cb0,stroke:#1a365d,color:#fff;
    classDef io fill:#e2e8f0,stroke:#94a3b8,color:#1a202c;
    class RP,T8 chip;
    class USB,VBUS,LED,SW,H,PSU io;

Loading

The RP2350 is the configuration master: it loads the Trion T8 bitstream over a passive SPI link and drives CRESET / oscillator enable, while CDONE and nSTATUS report back. Most of the FPGA fabric is broken out to the Teensy header; the RP2350 owns the two UARTs on pins 0/1 and 7/8.

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Board pinout (Teensy 4.0 form factor)

The two 14-pin side headers follow the Teensy 4.0 layout (top view, USB at the top edge). Digital pins 0..23 are routed either to the RP2350 or to the Trion T8 fabric.

Physical connector layout (top view, USB at the top edge):

Left function	Left pin		Right pin	Right function
GND	GND		VIN	VIN
UART1 RX	0		GND	GND
UART1 TX	1		3V3	+3V3
RP2350 GPIO22	2		23	T8 E2
RP2350 GPIO23	3		22	T8 D2
T8 A5	4		21	T8 C2
T8 D7	5		20	T8 A3
T8 C7	6		19	T8 A7
UART0 TX	7		18	T8 B7
UART0 RX	8		17	T8 B3
T8 D6	9		16	T8 C6
T8 G7	10		15	T8 E5
T8 G5	11		14	T8 F6
T8 G2	12		13	T8 F5

Rear pads: 3V3 · VBAT · PROGRAM · ON/OFF · GND.

Digital pin functions

Teensy pin	Net	Goes to	Signal / function
0	RP.UART1_RX	RP2350 GPIO8	UART1 RX
1	RP.UART1_TX	RP2350 GPIO9	UART1 TX
2	PIN2	RP2350 GPIO22	RP2350 GPIO (header break-out)
3	PIN3	RP2350 GPIO23	RP2350 GPIO (header break-out)
4	PIN4	T8 A5	FPGA GPIO (GPIOR_05)
5	PIN5	T8 D7	FPGA GPIO (GPIOR_17_CTRL6)
6	PIN6	T8 C7	FPGA GPIO (GPIOR_16_CTRL7)
7	RP.UART0_TX	RP2350 GPIO12	UART0 TX
8	RP.UART0_RX	RP2350 GPIO13	UART0 RX
9	PIN9	T8 D6	FPGA GPIO (GPIOR_15_CBUS0)
10	PIN10	T8 G7	FPGA GPIO (GPIOR_37_TEST)
11	PIN11	T8 G5	FPGA GPIO (GPIOR_34_CSI)
12	PIN12	T8 G2	FPGA GPIO (GPIOL_03_CDI4)
13	PIN13	T8 F5	FPGA GPIO (GPIOR_24)
14	PIN14	T8 F6	FPGA GPIO (GPIOR_26_CBSEL0)
15	PIN15	T8 E5	FPGA GPIO (GPIOR_23_CTRL4)
16	PIN16	T8 C6	FPGA GPIO (GPIOR_13)
17	PIN17	T8 B3	FPGA GPIO (GPIOL_16_CLK2)
18	PIN18	T8 B7	FPGA GPIO (GPIOR_10)
19	PIN19	T8 A7	FPGA GPIO (GPIOR_07)
20	PIN20	T8 A3	FPGA GPIO (GPIOL_18_CTRL2)
21	PIN21	T8 C2	FPGA GPIO (GPIOL_12_CTRL0)
22	PIN22	T8 D2	FPGA GPIO (GPIOL_11_CDI3)
23	PIN23	T8 E2	FPGA GPIO (GPIOL_09_CDI2)

Trion T8 pins B3, C2, E5 (CLK2, CTRL0, CTRL4) sit on clock/control-capable banks — prefer these for clock or control inputs brought in from the header.

Power pins

Pin	Net	Description
VIN	VIN	5 V input (also fed from USB-C VBUS).
3V3	+3V3	3.3 V rail (TPS62162 buck) — I/O supply.
VBAT	—	Battery input (LM73100 ideal-diode / PPM).
GND	GND	Ground.

The Trion T8 core (+1V1) is generated on-board by a TPS7A20 LDO.

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RP2350 ↔ Trion T8 configuration interface

The RP2350 acts as the FPGA configuration master (passive SPI). These signals are internal to the board (not on the header):

RP2350	Signal	Trion T8 pin	T8 function
GPIO1	FPGA_CS	G3	GPIOL_01_SS
GPIO2	FPGA_CLK	F3	GPIOL_02_CCK
GPIO3	FPGA_MOSI	F2	GPIOL_04_CDI0
GPIO4	FPGA_nRESET	G4	CRESET
GPIO5	FPGA_DONE	F4	CDONE
GPIO6	FPGA_nSTATUS	A4	GPIOL_21_STATUS
GPIO19/20	FPGA_OSC_EN	—	Oscillator enable (Y2)

USB is the RP2350 native USB (USB_DP/USB_DM) on the USB-C connector, used both for the CDC bridge and for BOOTSEL programming of the RP2350.

On-board peripherals

• RGB LED (D1) driven by the Trion T8: R → E1 (GPIOL_10_CDI7), G → F1 (GPIOL_06_CDI1), B → G1 (GPIOL_05_CDI5).
• User push-button (SW1) on the Trion T8 right I/O bank (GPIOR_3x).
• 12 MHz crystal for the RP2350; a ECS-2520MV oscillator (Y2) clocks the T8.

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Programming via drag-and-drop

The firmware in rp2350_fw/src exposes the RP2350 as a FORGIX_T8 USB Mass Storage drive containing a single FIRMWARE.HEX file. Programming the Trion T8 is just a file copy:

# build once (see rp2350_fw/readme.md)
export PICO_SDK_PATH=/path/to/pico-sdk
scripts/build_fw.sh

# then just drag-and-drop, or from a terminal:
cp examples/blink_led/output/blink_led.hex /media/$USER/FORGIX_T8/FIRMWARE.HEX

The bitstream is streamed straight to SPI as it's written (no host software, no size limit tied to RP2350 RAM), with progress printed on the CDC serial port as it goes. Once DONE goes high, the FORGIX_T8 drive disappears and the CDC port becomes a raw passthrough bridge to the FPGA's UART0 (GPIO2 TX / GPIO3 RX for send/receive) — open it with any serial terminal.

To load a different bitstream afterward (no physical reset needed), use fpga_loader/reset_and_load.py: it sends a magic reset sequence over the CDC port, waits for FORGIX_T8 to reappear, and copies the new .hex onto it in one step:

cd fpga_loader
python -m pip install -r requirements.txt      # pyserial
python reset_and_load.py examples/blink_led/output/blink_led.hex

See rp2350_fw/readme.md for details.

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Board and schematic © Adiuvo Engineering. This repository holds accompanying example designs and firmware.