System Verilog Syllabus

Introduction
|
|-- Basics of SystemVerilog
|   |-- Data Types
|   |   |-- 1. Built-in Types (logic, bit, reg, etc.)
|   |   |-- 2. Vectors and Arrays
|   |   |-- 3. Packed and Unpacked Arrays
|   |
|   |-- Operators and Expressions
|   |   |-- 4. Arithmetic, Logical, Bitwise, Relational
|   |   |-- 5. Shift, Reduction, Concatenation
|   |   |-- 6. Conditional Expressions
|   |
|   |-- Procedural Blocks
|       |-- 7. Initial and Always Blocks
|       |-- 8. Assignments (blocking, non-blocking)
|       |-- 9. Timing Control (delay, event control)
|
|-- Control Flow
|   |-- 10. Conditional Statements (if-else, case)
|   |-- 11. Loops (for, while, repeat, forever)
|   |-- 12. Special Constructs (unique, priority, foreach)
|
|-- Advanced Data Types
|   |-- 13. Structs and Unions
|   |-- 14. Enums and Typedef
|   |-- 15. Parameterized Types (type parameters, typedef)
|
|-- Interface and Modularity
|   |-- Interfaces and Modports
|   |-- Clocking Blocks
|   |-- Modules and Hierarchical Structures
|
|-- Assertions and Coverage
|   |-- Immediate and Concurrent Assertions
|   |-- SystemVerilog Assertions (SVA)
|   |-- Functional and Code Coverage


|
|-- Object-Oriented Programming (OOP) in SystemVerilog
|   |-- Classes and Objects
|   |-- Inheritance and Polymorphism
|   |-- Virtual Methods and Interfaces
|   |-- Dynamic Data Structures
|
|-- Verification Techniques
|   |-- Functional Verification Overview
|   |-- Constrained-Random Verification
|   |-- Scoreboarding and Coverage-Driven Verification
|
|-- Universal Verification Methodology (UVM)
|   |-- UVM Basics and Testbench Architecture
|   |-- UVM Components (agents, drivers, monitors)
|   |-- Sequences and Transactions
|   |-- UVM Reporting and Messaging
|   |-- UVM Configuration and Factory Pattern
|
|-- SystemVerilog for Design
|   |-- RTL Coding with SystemVerilog
|   |-- Synthesis Constructs and Guidelines
|   |-- Linting and Static Analysis

Conclusion
|-- SystemVerilog Best Practices
|-- Resources and Further Learning