[pull] master from u-boot:master

arch/arc/lib/Makefile

@@ -12,6 +12,6 @@ obj-y += reset.o
 obj-y += ints_low.o
 obj-y += init_helpers.o
 
-obj-$(CONFIG_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
 
 lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _millicodethunk.o libgcc2.o

arch/arm/lib/Makefile

@@ -31,7 +31,7 @@ endif
 obj-$(CONFIG_CPU_V7M) += cmd_boot.o
 obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
 obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
-obj-$(CONFIG_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o
 else
 obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o

arch/m68k/lib/Makefile

@@ -8,7 +8,7 @@
 lib-$(CONFIG_USE_PRIVATE_LIBGCC) += lshrdi3.o muldi3.o ashldi3.o ashrdi3.o
 
 obj-y	+= bdinfo.o
-obj-$(CONFIG_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= cache.o
 obj-y	+= interrupts.o
 obj-y	+= time.o

arch/microblaze/lib/Makefile

@@ -3,6 +3,6 @@
 # (C) Copyright 2003-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
-obj-$(CONFIG_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BDI) += bdinfo.o
 obj-y	+= muldi3.o

arch/mips/lib/Makefile

@@ -10,7 +10,7 @@ obj-y	+= reloc.o
 obj-y	+= stack.o
 obj-y	+= traps.o
 
-obj-$(CONFIG_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-$(CONFIG_SPL_BUILD) += spl.o
 

arch/nios2/lib/Makefile

@@ -4,5 +4,5 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
 obj-y	+= cache.o
-obj-$(CONFIG_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= libgcc.o

arch/powerpc/cpu/mpc8xx/cpu_init.c

@@ -92,6 +92,12 @@ void cpu_init_f(immap_t __iomem *immr)
 				CONFIG_SYS_PLPRCR);
 #endif
 
+	/* Set SDMA configuration register */
+	if (IS_ENABLED(CONFIG_MPC885))
+		out_be32(&immr->im_siu_conf.sc_sdcr, 0x0040);
+	else
+		out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);
+
 	/*
 	 * Memory Controller:
 	 */

arch/powerpc/dts/cmpc885.dts

@@ -83,13 +83,23 @@
 		spi: spi@aa0 {
 			status = "okay";
 			#address-cells = <1>;
-			#size-cells = <1>;
-			cell-index = <0>;
+			#size-cells = <0>;
 			compatible = "fsl,mpc8xx-spi";
-			gpios = <&CPM1_PIO_B 21 1>; /* /EEPROM_CS ACTIVE_LOW */
+			gpios = <&CPM1_PIO_B 21 1	/* /EEPROM_CS ACTIVE_LOW */
+				 &CPM1_PIO_B 23 1	/* Temperature mother board */
+				 &CPM1_PIO_B 14 1>;	/* Temperature CPU board */
 
 			eeprom@0 {
-				cell-index = <1>;
+				reg = <0>;
+				compatible = "atmel,at25", "cs,eeprom";
+			};
+			temp@1 {
+				reg = <1>;
+				compatible = "ti,lm74";
+			};
+			temp@2 {
+				reg = <2>;
+				compatible = "ti,lm74";
 			};
 		};
 	};

arch/powerpc/dts/cmpcpro.dts

@@ -140,11 +140,21 @@
 			compatible = "fsl,mpc832x-spi";
 			reg = <0x4c0 0x40>;
 			mode = "cpu";
-			gpios = <&qe_pio_d 3 1>;
+			gpios = <&qe_pio_d 3 1
+				 &qe_pio_c 5 1		/* TEMP mother board */
+				 &qe_pio_c 3 1>;	/* TEMP CPU board */
 			clock-frequency = <0>;
-			eeprom@3 {
+			eeprom@0 {
+				reg = <0>;
 				compatible = "atmel,at25", "cs,eeprom";
-				cell-index = <1>;
+			};
+			temp@1 {
+				reg = <1>;
+				compatible = "ti,lm74";
+			};
+			temp@2 {
+				reg = <2>;
+				compatible = "ti,lm74";
 			};
 		};
 		eth0: ucc@3000 {

arch/powerpc/dts/mcr3000.dts

@@ -26,6 +26,47 @@
 			timeout-sec = <2>;
 			hw_margin_ms = <1000>;
 		};
+
+		spi: spi@aa0 {
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl,mpc8xx-spi";
+			gpios = <&csspi 2 0
+				 &csspi 0 0>;
+
+			temp@0 {
+				reg = <0>;
+				compatible = "ti,lm74";
+			};
+			fpga@1 {
+				reg = <1>;
+			};
+		};
+	};
+
+	localbus@ff000100 {
+		compatible = "s3k,mcr3000-localbus", "fsl,pq1-localbus", "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		reg = <0xff000100 0x40>;		// ORx and BRx register
+
+		ranges = <0 0 0x04000000 0x04000000 // BOOT
+			  1 0 0x00000000 0x04000000 // SDRAM
+			  2 0 0x08000000 0x04000000 // RAMDP
+			  3 0 0x0C000000 0x04000000 // NAND
+			  4 0 0x10000000 0x04000000 // Periphs
+			  5 0 0x14000000 0x04000000 // FPGA
+			  6 0 0x18000000 0x04000000 // mezzanine
+			  7 0 0x1c000000 0x04000000>; // DSP
+
+		csspi: gpio-controller@2 {
+			#gpio-cells = <2>;
+			compatible = "s3k,mcr3000-cpld-csspi";
+			reg = <4 0x802 2>;
+			gpio-controller;
+		};
 	};
 
 	SERIAL: smc@0 {

arch/powerpc/lib/Makefile

@@ -34,7 +34,7 @@ obj-y	+= ticks.o
 endif
 obj-y	+= reloc.o
 
-obj-$(CONFIG_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= cache.o
 obj-y	+= extable.o
 obj-y	+= interrupts.o

arch/riscv/lib/Makefile

@@ -6,7 +6,7 @@
 # Copyright (C) 2017 Andes Technology Corporation
 # Rick Chen, Andes Technology Corporation <rick@andestech.com>
 
-obj-$(CONFIG_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-y	+= cache.o

arch/sandbox/lib/Makefile

@@ -7,5 +7,5 @@
 
 obj-y	+= fdt_fixup.o interrupts.o sections.o
 obj-$(CONFIG_PCI)	+= pci_io.o
-obj-$(CONFIG_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTZ) += bootm.o

arch/sh/lib/Makefile

@@ -6,7 +6,7 @@
 extra-y	+= start.o
 
 obj-y	+= board.o
-obj-$(CONFIG_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= time.o
 obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o
 

arch/x86/lib/Makefile

@@ -16,7 +16,7 @@ obj-$(CONFIG_X86_32BIT_INIT) += string.o
 endif
 
 ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
 endif
 obj-y	+= cmd_boot.o
 obj-$(CONFIG_$(SPL_)COREBOOT_SYSINFO)	+= coreboot/

arch/x86/lib/spl.c

@@ -283,7 +283,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 {
 	int ret;
 
-	printf("Jumping to 64-bit U-Boot\n");
+	printf("Jumping to 64-bit U-Boot: Note many features are missing\n");
 	ret = cpu_jump_to_64bit_uboot(spl_image->entry_point);
 	debug("ret=%d\n", ret);
 	hang();

arch/xtensa/lib/Makefile

@@ -3,6 +3,6 @@
 # (C) Copyright 2007 - 2013 Tensilica Inc.
 # (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
 
-obj-$(CONFIG_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
 
 obj-y	+= cache.o misc.o relocate.o time.o

board/cssi/cmpc885/Makefile

@@ -5,6 +5,6 @@
 # Christophe Leroy <christophe.leroy@c-s.fr>
 #
 
-obj-y += cmpc885.o ../common/common.o
+obj-y += cmpc885.o
 obj-y += sdram.o
 obj-$(CONFIG_CMD_NAND) += nand.o

board/cssi/cmpc885/cmpc885.c

@@ -114,8 +114,10 @@ static int setup_mac(void)
 	if (memcmp(din + EE_OFF_MAC1, &ident, sizeof(ident)) == 0)
 		eth_env_set_enetaddr("ethaddr", din + EE_OFF_MAC1);
 
-	if (memcmp(din + EE_OFF_MAC2, &ident, sizeof(ident)) == 0)
+	if (memcmp(din + EE_OFF_MAC2, &ident, sizeof(ident)) == 0) {
 		eth_env_set_enetaddr("eth1addr", din + EE_OFF_MAC2);
+		eth_env_set_enetaddr("eth2addr", din + EE_OFF_MAC2);
+	}
 
 	return 0;
 }

board/cssi/cmpc885/cmpc885.env

@@ -2,6 +2,6 @@ loadaddr=0x1a00000
 filename=cmpc885.itb
 console_args=console=ttyCPM0,115200N8
 loadkernel=ubi part nand0;ubifsmount ubi0;ubifsload ${loadaddr} /boot/${filename};ubifsumount; ubi detach
-flashboot=setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; run loadkernel; bootm $loadaddr#$config
-tftpboot=setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; tftp ${loadaddr} ${filename};bootm $loadaddr#$config
+flashboot=setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; run loadkernel; bootm ${loadaddr}#${config}
+tftpboot=setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; tftp ${loadaddr} ${filename};bootm ${loadaddr}#${config}
 update=echo 'Updating ubi image'; if tftp $loadaddr $ubifile; then nand erase.chip; nand write $loadaddr 0x00 $filesize; fi;

board/cssi/cmpcpro/Makefile

@@ -5,4 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += cmpcpro.o nand.o ../common/common.o
+obj-y += cmpcpro.o nand.o

board/cssi/cmpcpro/cmpcpro.env

@@ -3,6 +3,6 @@ filename=cmpcpro.itb
 netdev=eth0
 console_args=console=ttyS0,115200N8
 loadkernel=ubi part nand0;ubifsmount ubi0; ubifsload ${loadaddr} /boot/${filename}; ubifsumount; ubi detach
-flashboot=mw.w 90000040 0x000E 1; setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; run loadkernel; bootm $loadaddr#$config
-tftpboot=mw.w 90000040 0x000E 1; setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; tftp ${loadaddr} ${filename}; bootm $loadaddr#$config
+flashboot=mw.w 90000040 0x000E 1; setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; run loadkernel; bootm ${loadaddr}#${config}
+tftpboot=mw.w 90000040 0x000E 1; setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; tftp ${loadaddr} ${filename}; bootm ${loadaddr}#${config}
 update=echo 'Updating ubi image'; mw.w 90000040 0x000E 1; if tftp $loadaddr $ubifile; then nand erase.chip; nand write $loadaddr 0x00 $filesize; fi;

board/cssi/common/Makefile

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 CS GROUP France
+# Christophe Leroy <christophe.leroy@csgroup.eu>
+#
+
+obj-$(CONFIG_TARGET_CMPC885) += common.o
+obj-$(CONFIG_TARGET_CMPCPRO) += common.o

board/cssi/common/common.c

@@ -164,7 +164,7 @@ int checkboard_common(void)
 
 void misc_init_r_common(void)
 {
-	u8 tmp, far_id;
+	u8 tmp, far_id, addr;
 	int count = 3;
 
 	switch (in_8(ADDR_FPGA_R_BASE)) {
@@ -173,6 +173,10 @@ void misc_init_r_common(void)
 		if ((in_8(ADDR_FPGA_R_BASE + 0x31) & FPGA_R_ACQ_AL_FAV) == 0)
 			env_set("bootdelay", "60");
 
+		addr = in_8(ADDR_FPGA_R_BASE + 0x43);
+		printf("Board address: 0x%2.2x (System %d Rack %d Slot %d)\n",
+		       addr, addr >> 7, (addr >> 4) & 7, addr & 15);
+
 		env_set("config", CFG_BOARD_MCR3000_2G);
 		env_set("hostname", CFG_BOARD_MCR3000_2G);
 		break;
@@ -208,12 +212,44 @@ void misc_init_r_common(void)
 	}
 }
 
+static void iop_setup_fpgam_common(void)
+{
+	u8 far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
+
+	if (far_id == FAR_CASRSA) {
+		/*
+		 * PFDIR[15]  = 0 [0x01]
+		 * PFDIR[14]  = 1 [0x02]
+		 * PFDIR[13]  = 1 [0x04]
+		 */
+		clrsetbits_8(ADDR_FPGA_R_BASE + 0x37, 0x01, 0x06);
+		/*
+		 * PFODR[15]  = 1 [0x01]
+		 * PFODR[14]  = 0 [0x02]
+		 * PFODR[13]  = 0 [0x04]
+		 */
+		clrsetbits_8(ADDR_FPGA_R_BASE + 0x39, 0x06, 0x01);
+		/*
+		 * PFDAT[15]  = 0 [0x01]
+		 * PFDAT[14]  = 1 [0x02]
+		 * PFDAT[13]  = 1 [0x04]
+		 * PFDAT[12]  = 1 [0x08]
+		 */
+		clrsetbits_8(ADDR_FPGA_R_BASE + 0x3B, 0x01, 0x0E);
+
+		/* Setup TOR_OUT */
+		out_8(ADDR_FPGA_R_BASE + 0x32, 0x2A);
+	}
+}
+
 void iop_setup_common(void)
 {
 	u8 type = in_8(ADDR_FPGA_R_BASE);
 
-	if (type == TYPE_MCR)
+	if (type == TYPE_MCR) {
 		iop_setup_mcr();
-	else if (type == TYPE_MIAE)
+	} else if (type == TYPE_MIAE) {
 		iop_setup_miae();
+		iop_setup_fpgam_common();
+	}
 }

board/cssi/mcr3000/Makefile

@@ -6,3 +6,4 @@
 
 obj-y += mcr3000.o
 obj-$(CONFIG_CMD_NAND) += nand.o
+obj-$(CONFIG_MPC8XX_SPI) += mcr3000_gpio.o