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crypto: qat - Intel(R) QAT DH895xcc accelerator
This patch adds DH895xCC hardware specific code. It hooks to the common infrastructure and provides acceleration for crypto algorithms. Acked-by: John Griffin <john.griffin@intel.com> Reviewed-by: Bruce W. Allan <bruce.w.allan@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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‎drivers/crypto/qat/qat_dh895xcc/Makefile‎

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ccflags-y := -I$(CURDIR)/drivers/crypto/qat/qat_common
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obj-$(CONFIG_CRYPTO_DEV_QAT_DH895xCC) += qat_dh895xcc.o
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qat_dh895xcc-objs := adf_drv.o \
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adf_isr.o \
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adf_dh895xcc_hw_data.o \
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adf_hw_arbiter.o \
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qat_admin.o \
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adf_admin.o

‎drivers/crypto/qat/qat_dh895xcc/adf_admin.c‎

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/*
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This file is provided under a dual BSD/GPLv2 license. When using or
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redistributing this file, you may do so under either license.
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GPL LICENSE SUMMARY
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Copyright(c) 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of version 2 of the GNU General Public License as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Contact Information:
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qat-linux@intel.com
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BSD LICENSE
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Copyright(c) 2014 Intel Corporation.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/types.h>
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#include <linux/mutex.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <adf_accel_devices.h>
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#include "adf_drv.h"
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#include "adf_dh895xcc_hw_data.h"
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#define ADF_ADMINMSG_LEN 32
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struct adf_admin_comms {
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dma_addr_t phy_addr;
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void *virt_addr;
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void __iomem *mailbox_addr;
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struct mutex lock; /* protects adf_admin_comms struct */
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};
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int adf_put_admin_msg_sync(struct adf_accel_dev *accel_dev,
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uint32_t ae, void *in, void *out)
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{
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struct adf_admin_comms *admin = accel_dev->admin;
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int offset = ae * ADF_ADMINMSG_LEN * 2;
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void __iomem *mailbox = admin->mailbox_addr;
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int mb_offset = ae * ADF_DH895XCC_MAILBOX_STRIDE;
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int times, received;
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mutex_lock(&admin->lock);
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if (ADF_CSR_RD(mailbox, mb_offset) == 1) {
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mutex_unlock(&admin->lock);
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return -EAGAIN;
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}
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memcpy(admin->virt_addr + offset, in, ADF_ADMINMSG_LEN);
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ADF_CSR_WR(mailbox, mb_offset, 1);
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received = 0;
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for (times = 0; times < 50; times++) {
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msleep(20);
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if (ADF_CSR_RD(mailbox, mb_offset) == 0) {
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received = 1;
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break;
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}
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}
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if (received)
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memcpy(out, admin->virt_addr + offset +
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ADF_ADMINMSG_LEN, ADF_ADMINMSG_LEN);
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else
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pr_err("QAT: Failed to send admin msg to accelerator\n");
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mutex_unlock(&admin->lock);
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return received ? 0 : -EFAULT;
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}
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int adf_init_admin_comms(struct adf_accel_dev *accel_dev)
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{
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struct adf_admin_comms *admin;
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struct adf_bar *pmisc = &GET_BARS(accel_dev)[ADF_DH895XCC_PMISC_BAR];
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void __iomem *csr = pmisc->virt_addr;
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void __iomem *mailbox = csr + ADF_DH895XCC_MAILBOX_BASE_OFFSET;
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uint64_t reg_val;
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admin = kzalloc_node(sizeof(*accel_dev->admin), GFP_KERNEL,
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accel_dev->numa_node);
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if (!admin)
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return -ENOMEM;
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admin->virt_addr = dma_zalloc_coherent(&GET_DEV(accel_dev), PAGE_SIZE,
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&admin->phy_addr, GFP_KERNEL);
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if (!admin->virt_addr) {
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dev_err(&GET_DEV(accel_dev), "Failed to allocate dma buff\n");
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kfree(admin);
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return -ENOMEM;
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}
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reg_val = (uint64_t)admin->phy_addr;
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ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGUR_OFFSET, reg_val >> 32);
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ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGLR_OFFSET, reg_val);
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mutex_init(&admin->lock);
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admin->mailbox_addr = mailbox;
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accel_dev->admin = admin;
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return 0;
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}
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void adf_exit_admin_comms(struct adf_accel_dev *accel_dev)
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{
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struct adf_admin_comms *admin = accel_dev->admin;
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if (!admin)
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return;
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if (admin->virt_addr)
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dma_free_coherent(&GET_DEV(accel_dev), PAGE_SIZE,
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admin->virt_addr, admin->phy_addr);
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mutex_destroy(&admin->lock);
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kfree(admin);
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accel_dev->admin = NULL;
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}

‎drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c‎

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/*
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This file is provided under a dual BSD/GPLv2 license. When using or
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redistributing this file, you may do so under either license.
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GPL LICENSE SUMMARY
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Copyright(c) 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify
8+
it under the terms of version 2 of the GNU General Public License as
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published by the Free Software Foundation.
10+
11+
This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Contact Information:
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qat-linux@intel.com
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BSD LICENSE
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Copyright(c) 2014 Intel Corporation.
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Redistribution and use in source and binary forms, with or without
22+
modification, are permitted provided that the following conditions
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are met:
24+
25+
* Redistributions of source code must retain the above copyright
26+
notice, this list of conditions and the following disclaimer.
27+
* Redistributions in binary form must reproduce the above copyright
28+
notice, this list of conditions and the following disclaimer in
29+
the documentation and/or other materials provided with the
30+
distribution.
31+
* Neither the name of Intel Corporation nor the names of its
32+
contributors may be used to endorse or promote products derived
33+
from this software without specific prior written permission.
34+
35+
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36+
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37+
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
38+
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
39+
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
40+
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
41+
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
42+
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
43+
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <adf_accel_devices.h>
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#include "adf_dh895xcc_hw_data.h"
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#include "adf_drv.h"
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/* Worker thread to service arbiter mappings based on dev SKUs */
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static const uint32_t thrd_to_arb_map_sku4[] = {
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0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
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0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
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0x00000000, 0x00000000, 0x00000000, 0x00000000
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};
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static const uint32_t thrd_to_arb_map_sku6[] = {
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0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
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0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
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0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222
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};
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static struct adf_hw_device_class dh895xcc_class = {
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.name = ADF_DH895XCC_DEVICE_NAME,
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.type = DEV_DH895XCC,
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.instances = 0
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};
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static uint32_t get_accel_mask(uint32_t fuse)
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{
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return (~fuse) >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET &
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ADF_DH895XCC_ACCELERATORS_MASK;
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}
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static uint32_t get_ae_mask(uint32_t fuse)
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{
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return (~fuse) & ADF_DH895XCC_ACCELENGINES_MASK;
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}
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static uint32_t get_num_accels(struct adf_hw_device_data *self)
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{
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uint32_t i, ctr = 0;
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if (!self || !self->accel_mask)
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return 0;
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for (i = 0; i < ADF_DH895XCC_MAX_ACCELERATORS; i++) {
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if (self->accel_mask & (1 << i))
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ctr++;
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}
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return ctr;
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}
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static uint32_t get_num_aes(struct adf_hw_device_data *self)
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{
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uint32_t i, ctr = 0;
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if (!self || !self->ae_mask)
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return 0;
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for (i = 0; i < ADF_DH895XCC_MAX_ACCELENGINES; i++) {
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if (self->ae_mask & (1 << i))
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ctr++;
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}
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return ctr;
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}
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static uint32_t get_misc_bar_id(struct adf_hw_device_data *self)
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{
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return ADF_DH895XCC_PMISC_BAR;
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}
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static uint32_t get_etr_bar_id(struct adf_hw_device_data *self)
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{
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return ADF_DH895XCC_ETR_BAR;
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}
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static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
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{
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int sku = (self->fuses & ADF_DH895XCC_FUSECTL_SKU_MASK)
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>> ADF_DH895XCC_FUSECTL_SKU_SHIFT;
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switch (sku) {
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case ADF_DH895XCC_FUSECTL_SKU_1:
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return DEV_SKU_1;
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case ADF_DH895XCC_FUSECTL_SKU_2:
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return DEV_SKU_2;
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case ADF_DH895XCC_FUSECTL_SKU_3:
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return DEV_SKU_3;
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case ADF_DH895XCC_FUSECTL_SKU_4:
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return DEV_SKU_4;
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default:
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return DEV_SKU_UNKNOWN;
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}
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return DEV_SKU_UNKNOWN;
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}
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void adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev,
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uint32_t const **arb_map_config)
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{
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switch (accel_dev->accel_pci_dev.sku) {
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case DEV_SKU_1:
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*arb_map_config = thrd_to_arb_map_sku4;
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break;
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case DEV_SKU_2:
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case DEV_SKU_4:
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*arb_map_config = thrd_to_arb_map_sku6;
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break;
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default:
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pr_err("QAT: The configuration doesn't match any SKU");
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*arb_map_config = NULL;
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}
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}
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static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
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{
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struct adf_hw_device_data *hw_device = accel_dev->hw_device;
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struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_DH895XCC_PMISC_BAR];
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void __iomem *csr = misc_bar->virt_addr;
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unsigned int val, i;
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/* Enable Accel Engine error detection & correction */
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for (i = 0; i < hw_device->get_num_aes(hw_device); i++) {
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val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i));
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val |= ADF_DH895XCC_ENABLE_AE_ECC_ERR;
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ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val);
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val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i));
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val |= ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR;
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ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val);
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}
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/* Enable shared memory error detection & correction */
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for (i = 0; i < hw_device->get_num_accels(hw_device); i++) {
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val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i));
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val |= ADF_DH895XCC_ERRSSMSH_EN;
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ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val);
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val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i));
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val |= ADF_DH895XCC_ERRSSMSH_EN;
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ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val);
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}
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}
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void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
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{
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hw_data->dev_class = &dh895xcc_class;
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hw_data->instance_id = dh895xcc_class.instances++;
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hw_data->num_banks = ADF_DH895XCC_ETR_MAX_BANKS;
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hw_data->num_accel = ADF_DH895XCC_MAX_ACCELERATORS;
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hw_data->pci_dev_id = ADF_DH895XCC_PCI_DEVICE_ID;
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hw_data->num_logical_accel = 1;
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hw_data->num_engines = ADF_DH895XCC_MAX_ACCELENGINES;
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hw_data->tx_rx_gap = ADF_DH895XCC_RX_RINGS_OFFSET;
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hw_data->tx_rings_mask = ADF_DH895XCC_TX_RINGS_MASK;
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hw_data->alloc_irq = adf_isr_resource_alloc;
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hw_data->free_irq = adf_isr_resource_free;
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hw_data->enable_error_correction = adf_enable_error_correction;
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hw_data->hw_arb_ring_enable = adf_update_ring_arb_enable;
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hw_data->hw_arb_ring_disable = adf_update_ring_arb_enable;
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hw_data->get_accel_mask = get_accel_mask;
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hw_data->get_ae_mask = get_ae_mask;
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hw_data->get_num_accels = get_num_accels;
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hw_data->get_num_aes = get_num_aes;
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hw_data->get_etr_bar_id = get_etr_bar_id;
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hw_data->get_misc_bar_id = get_misc_bar_id;
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hw_data->get_sku = get_sku;
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hw_data->fw_name = ADF_DH895XCC_FW;
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}
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void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
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{
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hw_data->dev_class->instances--;
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}

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