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net: ethernet: mtk_eth_soc: convert clock bitmap to u64
The to-be-added MT7988 SoC adds many new clocks which need to be controlled by the Ethernet driver, which will result in their total number exceeding 32. Prepare by converting clock bitmaps into 64-bit types. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/6960a39bb0078cf84d7642a9558e6a91c6cc9df3.1690246066.git.daniel@makrotopia.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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‎drivers/net/ethernet/mediatek/mtk_eth_soc.h‎

Lines changed: 49 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -666,54 +666,56 @@ enum mtk_clks_map {
666666
MTK_CLK_MAX
667667
};
668668

669-
#define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
670-
BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
671-
BIT(MTK_CLK_TRGPLL))
672-
#define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
673-
BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
674-
BIT(MTK_CLK_GP2) | \
675-
BIT(MTK_CLK_SGMII_TX_250M) | \
676-
BIT(MTK_CLK_SGMII_RX_250M) | \
677-
BIT(MTK_CLK_SGMII_CDR_REF) | \
678-
BIT(MTK_CLK_SGMII_CDR_FB) | \
679-
BIT(MTK_CLK_SGMII_CK) | \
680-
BIT(MTK_CLK_ETH2PLL))
669+
#define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
670+
BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
671+
BIT_ULL(MTK_CLK_TRGPLL))
672+
#define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
673+
BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
674+
BIT_ULL(MTK_CLK_GP2) | \
675+
BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
676+
BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
677+
BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
678+
BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
679+
BIT_ULL(MTK_CLK_SGMII_CK) | \
680+
BIT_ULL(MTK_CLK_ETH2PLL))
681681
#define MT7621_CLKS_BITMAP (0)
682682
#define MT7628_CLKS_BITMAP (0)
683-
#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
684-
BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
685-
BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
686-
BIT(MTK_CLK_SGMII_TX_250M) | \
687-
BIT(MTK_CLK_SGMII_RX_250M) | \
688-
BIT(MTK_CLK_SGMII_CDR_REF) | \
689-
BIT(MTK_CLK_SGMII_CDR_FB) | \
690-
BIT(MTK_CLK_SGMII2_TX_250M) | \
691-
BIT(MTK_CLK_SGMII2_RX_250M) | \
692-
BIT(MTK_CLK_SGMII2_CDR_REF) | \
693-
BIT(MTK_CLK_SGMII2_CDR_FB) | \
694-
BIT(MTK_CLK_SGMII_CK) | \
695-
BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
696-
#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
697-
BIT(MTK_CLK_WOCPU0) | \
698-
BIT(MTK_CLK_SGMII_TX_250M) | \
699-
BIT(MTK_CLK_SGMII_RX_250M) | \
700-
BIT(MTK_CLK_SGMII_CDR_REF) | \
701-
BIT(MTK_CLK_SGMII_CDR_FB) | \
702-
BIT(MTK_CLK_SGMII2_TX_250M) | \
703-
BIT(MTK_CLK_SGMII2_RX_250M) | \
704-
BIT(MTK_CLK_SGMII2_CDR_REF) | \
705-
BIT(MTK_CLK_SGMII2_CDR_FB) | \
706-
BIT(MTK_CLK_SGMII_CK))
707-
#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
708-
BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
709-
BIT(MTK_CLK_SGMII_TX_250M) | \
710-
BIT(MTK_CLK_SGMII_RX_250M) | \
711-
BIT(MTK_CLK_SGMII_CDR_REF) | \
712-
BIT(MTK_CLK_SGMII_CDR_FB) | \
713-
BIT(MTK_CLK_SGMII2_TX_250M) | \
714-
BIT(MTK_CLK_SGMII2_RX_250M) | \
715-
BIT(MTK_CLK_SGMII2_CDR_REF) | \
716-
BIT(MTK_CLK_SGMII2_CDR_FB))
683+
#define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
684+
BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
685+
BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \
686+
BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
687+
BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
688+
BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
689+
BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
690+
BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
691+
BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
692+
BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
693+
BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
694+
BIT_ULL(MTK_CLK_SGMII_CK) | \
695+
BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP))
696+
#define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
697+
BIT_ULL(MTK_CLK_GP1) | \
698+
BIT_ULL(MTK_CLK_WOCPU0) | \
699+
BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
700+
BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
701+
BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
702+
BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
703+
BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
704+
BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
705+
BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
706+
BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
707+
BIT_ULL(MTK_CLK_SGMII_CK))
708+
#define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
709+
BIT_ULL(MTK_CLK_GP1) | \
710+
BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \
711+
BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
712+
BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
713+
BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
714+
BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
715+
BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
716+
BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
717+
BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
718+
BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
717719

718720
enum mtk_dev_state {
719721
MTK_HW_INIT,
@@ -1046,7 +1048,7 @@ struct mtk_soc_data {
10461048
const struct mtk_reg_map *reg_map;
10471049
u32 ana_rgc3;
10481050
u64 caps;
1049-
u32 required_clks;
1051+
u64 required_clks;
10501052
bool required_pctl;
10511053
u8 offload_version;
10521054
u8 hash_offset;

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