Update from dev.#27
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malcolmmackay merged 8 commits intomasterfrom May 4, 2021
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Updating from master.
This accomodates a transition to LPM3.5 each minute (to save power). After the RTC causes LPM3.5 to exit, a reset occurs and RAM is erased.
420nA current draw has been verified.
It occurs after every power up as a battery is inserted. https://e2e.ti.com/support/microcontrollers/msp430/f/msp-low-power-microcontroller-forum/296435/msp430f6438-sysrstiv-register https://e2e.ti.com/support/microcontrollers/msp430/f/msp-low-power-microcontroller-forum/132372/msp4305438-reset-problem
The capability container is no longer updated in n3th_check_address, unless the I2C slave address is not as expected.
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