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Stacked Terminal Interconnect Check is a program that checks the correspondence of terminals on stacked chips. Terminals are also referred to as pins or ports.

Inputs

• XML file to specify file names and port definitions.
• Virtual top level CDL netlist to specify the electrical correspondence of pins between chips.
• CDL netlists for each chip.
• GDS data for each chip.

Output

• CSV file listing check result, top level port name, port type, port center, and corresponding port on each chip.

Port Recognition

• Ports are simple layout cells with a port recognition layer.
• The origin of the port cell is the center of the port.
• Ports are named by text on the top layout of each chip.
• The layout cell determines the port type.

Port Definition

• There are 2 classifications of terminals: COIL and CONTACT. CONTACT terminals may be TSV or BUMP.
• COIL terminals must have the same winding direction, but are not required on every chip. COIL ports must be unique on each chip.
• TSV terminals have connections on the top and bottom of the chip, and must be connected on both sides to TSV or BUMP terminals. (The TSV connection can be an unlabeled through connection).
• BUMP terminals only have connections on the top and must be connected to TSV or BUMP terminals.
• Each port definition may have a corresponding text type. Top level text within the port recognition layer is assigned to the corresponding port.
• Each port type has its own tolerance. COIL ports are checked across all chips, while CONTACT ports are checked relative to the adjoining chip or absolute from the first chip.