Fail to parse `inside` expression in module-level if generate construct

[pointerliu]

The sv-parser parser fails to parse inside expressions when used in an if statement at module level (without explicit generate block), treating it as a generate construct.

Description

When parsing the following SystemVerilog code :

module a;
    typedef enum logic {
        SwAccessRW  = 0,
        SwAccessRO  = 1
    } sw_access_e;
    parameter sw_access_e SwAccess = SwAccessRW;
    wire x;
    if (SwAccess inside {SwAccessRW, SwAccessRO});
endmodule

The parser fails with an error at the inside keyword:

parse failed: "test_inside.sv"
 test_inside.sv:8:18
  |
8 |     if (SwAccess inside {SwAccessRW, SwAccessRO});
  |                  ^

Environment

• sv-parser version: 0.13.4