Dr Robotnik's Mean Bean Machine (FPGA)

An FPGA game for the Nexys A7-100T implementing the famous retro game - Dr. Robotnik's Mean Bean Machine, on VGA and shows score on the 7‑segment display.

Overview

• VGA output at 640x480@60 Hz (25 MHz pixel clock derived from 100 MHz).
• 6x12 game grid with 2‑bean pieces, rotation, locking, clears, gravity, and chains.
• 4 colors of beans with simple BFS-based group clearing (4+ connected).
• Score displayed on the 7‑segment display (6 digits with a thousands separator).

Controls (Nexys A7 switches)

• sw[0] move left
• sw[1] move right
• sw[2] rotate (clockwise)
• sw[3] soft drop
• sw[15] reset

Files

• rtl/top.sv — Top-level wiring, clock divide, and I/O.
• rtl/game_core.sv — Game state machine, RNG, clearing, gravity, scoring.
• rtl/renderer.sv — VGA renderer and HUD text/score drawing.
• rtl/vga_timing.sv — 640x480 timing generator + frame tick.
• rtl/sevenseg.sv — 32-bit to 6‑digit BCD + 7‑segment multiplexing.
• rtl/lfsr.sv — 16‑bit LFSR RNG.
• Nexys-A7100T-Master.xdc — Pin constraints for Nexys A7-100T.

Notes

• VGA is 4‑bit per channel (RGB444).
• Score increments by clear_count * 10 * (chain_count + 1).