🔲 4×4 Systolic Array Accelerator

Design & Verification of a Weight-Stationary Systolic Array with AXI4-Lite Interface

A fully verified systolic array accelerator for 4×4 matrix multiplication using IEEE 754 double-precision arithmetic. The project demonstrates the complete RTL-to-verification lifecycle using industry-standard tools and methodologies.

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📋 Key Metrics

Metric	Value
Array Size	4×4 (16 PEs)
Data Width	64-bit IEEE 754 double
Interface	AXI4-Lite (12-bit addr, 64-bit data)
Computation Latency	~40 cycles
Functional Coverage	100% (6 covergroups)
Code Coverage	100% (line/cond/FSM/tgl/branch)
SVA Assertions	38 (0 failures)
UVM Test Count	102 across 3 regression suites
Result Comparisons	1,632 pass / 0 fail

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🏗️ Architecture

                    ┌─────────────────────────────────┐
                    │        accelerator_top           │
                    │                                  │
  AXI4-Lite  ◄────►│  axi4_lite_slave ──► Reg File    │
  (Host CPU)       │                     ┌──────────┐ │
                    │  main_fsm ────────►│ Systolic  │ │
                    │    │               │  Array    │ │
                    │    ▼               │  4×4 PEs  │ │──► irq_done
                    │  skew_buffer ─────►│  (FMA)    │ │
                    │                     └──────────┘ │
                    └─────────────────────────────────┘

FSM States

IDLE → LOAD_WEIGHTS (16 cycles) → EXECUTE (23 cycles) → DONE (1 cycle) → IDLE

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📁 Project Structure

├── rtl/                           # Synthesizable RTL
│   ├── pkg/sa_pkg.sv              # Parameters, types, constants
│   ├── accelerator_top.sv         # Top-level integration
│   ├── axi4_lite_slave.sv         # AXI4-Lite slave interface
│   ├── main_fsm.sv                # 4-state control FSM
│   ├── systolic_array_core.sv     # 4×4 PE grid
│   ├── processing_element.sv      # Weight-stationary PE
│   ├── fp_fma.v                   # IEEE 754 fused multiply-add
│   ├── skew_buffer.sv             # Activation timing alignment
│   └── sram_dp.sv                 # Dual-port SRAM (unused)
│
├── tb/
│   ├── uvm/                       # UVM Verification Environment
│   │   ├── sa_env_pkg.sv          # Environment package
│   │   ├── sa_axi_if.sv           # AXI interface
│   │   ├── sa_sequence_item.sv    # Transaction item
│   │   ├── sa_driver.sv           # AXI transaction driver
│   │   ├── sa_scoreboard.sv       # IEEE 754-aware golden model
│   │   ├── sa_coverage.sv         # 6 covergroups
│   │   ├── sa_sequence.sv         # Base sequences
│   │   ├── sa_cov_sequences.sv    # 21 directed sequences
│   │   ├── sa_agent.sv            # Agent wrapper
│   │   ├── sa_env.sv              # Environment
│   │   ├── sa_test.sv             # Test classes
│   │   ├── tb_top.sv              # Testbench top
│   │   └── cov_exclude.el         # Coverage exclusion file
│   │
│   └── sva/                       # Formal Verification (SVA)
│       ├── sva_axi4_lite.sv       # 16 AXI protocol assertions
│       ├── sva_main_fsm.sv        # 18 FSM correctness assertions
│       ├── sva_accelerator_top.sv # 5 integration assertions
│       └── sva_bind.sv            # Non-invasive bind file
│
├── docs/
│   └── ARCHITECTURE.md            # Design documentation
│
└── Makefile                       # Build & regression automation

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🚀 Quick Start

Prerequisites

• Synopsys VCS (U-2023.03 or later) with UVM library

Run Commands

# Basic UVM regression (identity + matmul + 10 random)
make uvm

# Full coverage run (100% closure)
make cov_full

# SVA assertion checking
make uvm_sva

# Full SVA + Coverage regression (3 runs)
make sva_cov_full

# Clean all artifacts
make clean

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✅ Verification Summary

UVM Environment

• Driver: AXI4-Lite transaction driver with staggered write support
• Scoreboard: IEEE 754-aware golden model (NaN/Inf/subnormal handling)
• Coverage: 6 covergroups — weight bins, activation bins, result bins, matrix patterns, W×A cross-coverage, AXI protocol modes
• Sequences: 21 directed sequences targeting:
  • IEEE 754 edge cases (NaN, ±Inf, subnormals, Inf×0)
  • AXI protocol corners (staggered AW/W, register readback)
  • Cross-coverage filling (all 16 W×A type combinations)

SVA Formal Verification

• 38 assertions across 3 bind modules:
  • AXI4-Lite: Handshake stability, reset behavior, response codes
  • FSM: Legal transitions, counter bounds, timing constraints
  • Top-level: Start pulse, IRQ correctness, result conflict freedom, liveness
• 9 cover properties for reachability analysis
• All assertions pass across 102 regression tests

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🛠️ Tools & Technologies

Category	Tools
Language	SystemVerilog, Verilog
Methodology	UVM 1.1d, SVA
Simulator	Synopsys VCS U-2023.03
Coverage	VCS Coverage Metrics, URG
Protocol	AXI4-Lite (AMBA)
Arithmetic	IEEE 754 Double-Precision

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📊 Coverage Closure

Covergroup	Coverage
Weight Bins	100%
Activation Bins	100%
Result Bins	100%
Matrix Patterns	100%
W × A Cross	100%
AXI Protocol	100%
Code (line/cond/FSM/tgl/branch)	100%

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📄 License

This project is for educational and portfolio purposes.