[Intel-SIG] [Meteor Lake] Enable DRM feature with Intel MTL platform

[junxiaoc]

All patches in this PR have been upstreamed. These commits in PR have been tested with Deepin, MTLp hardware and related Linux firmwares. It works as expected.

Summary by Sourcery

Enable and stabilize Meteor Lake (MTL) support in the Intel i915 DRM driver by upstreaming and consolidating MTL‐specific feature enablement, workarounds, and refactorings. Add DSC helper routines, unify IP version checks, introduce GGTT bind contexts, and apply platform workarounds across display, power management, and fbdev subsystems.

New Features:

• Implement MTL display stream compression PPS write/read helpers to support multiple VDSC units per pipe
• Add separate GGTT bind context for platforms requiring hardware‐assisted PTE updates
• Expose a common display workaround hook to apply per‐platform WA sequences

Bug Fixes:

• Work around ATS/IOMMU issues on MTL by forcing WC mapping for PPGTT page table updates
• Ensure bind context readiness is toggled during GT suspend/resume to avoid races

Enhancements:

• Replace ad‐hoc MTL stepping macros with generic IP range/IP step checks
• Refactor DSC configuration to consolidate PPS register handling into helper functions
• Unify DDI voltage‐level, chicken‐register, and CDCLK selection across generations
• Simplify runtime PM and wakeref get/put logic for robust error handling
• Factor fbdev framebuffer creation into a standalone module

Chores:

• Add new files for display workarounds and fbdev framebuffer support and update Makefile
• Remove obsolete MTL subplatform enums and deprecated link_bit_rate fields
• Clean up stale code paths and redundant platform‐specific conditionals

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Hi @junxiaoc. Thanks for your PR. 😃

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[Avenger-285714]

@sourcery-ai review

[sourcery-ai]

Reviewer's Guide

This PR extends DRM support to Intel Meteor Lake by refactoring DSC picture-parameter-set handling into generic per-pipe write/read routines, unifying platform/stepping checks via new macros, introducing a GPU-bound context for GGTT updates on MTL, centralizing display workarounds, and modularizing fbdev allocation.

Class diagram for refactored DSC PPS handling

classDiagram
    class intel_crtc_state {
        +dsc: dsc_state
        +bigjoiner_pipes
        +cpu_transcoder
        +uapi
        +compressed_bpp
        +compression_enable
        +dsc_split
    }
    class dsc_state {
        +dsc_split
        +config: drm_dsc_config
    }
    class drm_dsc_config {
        +bits_per_component
        +line_buf_depth
        +block_pred_enable
        +convert_rgb
        +simple_422
        +native_422
        +native_420
        +vbr_enable
        +bits_per_pixel
        +pic_width
        +pic_height
        +slice_width
        +slice_height
        +initial_dec_delay
        +initial_xmit_delay
        +scale_decrement_interval
        +scale_increment_interval
        +initial_scale_value
        +first_line_bpg_offset
        +flatness_min_qp
        +flatness_max_qp
        +nfl_bpg_offset
        +slice_bpg_offset
        +initial_offset
        +final_offset
        +rc_model_size
        +rc_quant_incr_limit0
        +rc_quant_incr_limit1
        +slice_chunk_size
        +second_line_bpg_offset
        +nsl_bpg_offset
        +second_line_offset_adj
    }
    intel_crtc_state --> dsc_state
    dsc_state --> drm_dsc_config

    class intel_vdsc {
        +intel_dsc_get_vdsc_per_pipe()
        +intel_dsc_get_num_vdsc_instances()
        +intel_dsc_get_pps_reg()
        +intel_dsc_pps_write()
        +intel_dsc_pps_read()
        +intel_dsc_pps_read_and_verify()
        +intel_dsc_get_pps_config()
        +intel_dsc_pps_configure()
        +intel_dsc_enable()
        +intel_dsc_disable()
        +intel_dsc_get_config()
    }

Loading

Class diagram for unified platform/stepping macros

classDiagram
    class intel_gt {
        +type
        +i915
    }
    class drm_i915_private {
    }
    intel_gt --> drm_i915_private

    class PlatformMacros {
        +IS_GFX_GT_IP_RANGE(gt, from, until)
        +IS_MEDIA_GT_IP_RANGE(gt, from, until)
        +IS_GFX_GT_IP_STEP(gt, ipver, from, until)
        +IS_MEDIA_GT_IP_STEP(gt, ipver, from, until)
    }

Loading

File-Level Changes

Change	Details	Files
Refactor and generalize Display Stream Compression PPS handling	Extract per-pipe instance count into intel_dsc_get_vdsc_per_pipe Introduce intel_dsc_get_pps_reg and intel_dsc_pps_write for register writes Add intel_dsc_pps_read/_verify and intel_dsc_get_pps_config for state readback Replace repetitive direct writes with a loop over PPS indices	drivers/gpu/drm/i915/display/intel_vdsc.c drivers/gpu/drm/i915/display/intel_vdsc_regs.h
Unify stepping and platform checks with new IP‐range macros	Add IS_GFX_GT_IP_RANGE, IS_GFX_GT_IP_STEP, IS_MEDIA_GT_IP_RANGE, IS_DISPLAY_IP_STEP macros Replace scattered IS_METEORLAKE/IS_MTL_… usages with unified checks Remove old subplatform id tables and M/T/P variants	drivers/gpu/drm/i915/gt/intel_gt.h drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/intel_device_info.c
Implement GPU‐bound context for GGTT updates on Meteor Lake	Add create_ggtt_bind_context and bind_context field on BCS0 engine Introduce i915_ggtt_require_binder to gate bind submission Implement gen8_ggtt_bind_ptes and bind versions of insert_page/entries/scratch	drivers/gpu/drm/i915/gt/intel_engine_cs.c drivers/gpu/drm/i915/display/intel_ggtt.c drivers/gpu/drm/i915/gt/intel_gtt.h
Centralize display hardware workarounds into intel_display_wa.c	Move display chicken‐bit and DPFC WA into dedicated file Add intel_display_wa_apply and call it in init_hw Group per‐platform display WA routines under one entrypoint	drivers/gpu/drm/i915/display/intel_display_wa.c drivers/gpu/drm/i915/display/intel_display_driver.c
Modularize fbdev allocation and setup	Add intel_fbdev_fb_alloc and intel_fbdev_fb_fill_info helpers Split fbdev allocation logic into intel_fbdev_fb.c/.h Update intel_fbdev.c to call new abstraction	drivers/gpu/drm/i915/display/intel_fbdev.c drivers/gpu/drm/i915/display/intel_fbdev_fb.c

---

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[sourcery-ai]

Hey @junxiaoc - I've reviewed your changes - here's some feedback:

• The new intel_gt_mcr_lock_sanitize() helper is never called—add it to your GT init or resume path to ensure the hardware semaphore is in a known good state after firmware load.
• The bind_context_ready flag for the GGTT bind context must be set and cleared consistently across suspend/resume and engine teardown to avoid using an invalid context.
• There are still scattered uses of legacy IS_METEORLAKE/DISPLAY_VER checks in new MTL-specific code—consolidate to the new IS_GFX_GT_IP_* or IS_DISPLAY_IP_STEP macros for uniform stepping logic.

Prompt for AI Agents

Please address the comments from this code review:
## Overall Comments
- The new `intel_gt_mcr_lock_sanitize()` helper is never called—add it to your GT init or resume path to ensure the hardware semaphore is in a known good state after firmware load.
- The `bind_context_ready` flag for the GGTT bind context must be set and cleared consistently across suspend/resume and engine teardown to avoid using an invalid context.
- There are still scattered uses of legacy `IS_METEORLAKE`/`DISPLAY_VER` checks in new MTL-specific code—consolidate to the new `IS_GFX_GT_IP_*` or `IS_DISPLAY_IP_STEP` macros for uniform stepping logic.

## Individual Comments

### Comment 1
<location> `drivers/gpu/drm/i915/gt/intel_engine_cs.c:1421` </location>
<code_context>
 	intel_context_put(ce);
 }

+static struct intel_context *
+create_ggtt_bind_context(struct intel_engine_cs *engine)
+{
</code_context>

<issue_to_address>
The create_ggtt_bind_context function is only used for BCS0, but this is not enforced in the function itself.

Add an assertion or comment in create_ggtt_bind_context to clarify it should only be used with BCS0, preventing misuse with other engines.

Suggested implementation:

```c
static struct intel_context *
create_ggtt_bind_context(struct intel_engine_cs *engine)
{
	static struct lock_class_key kernel;

	/*
	 * This function is intended to be used only with the BCS0 engine.
	 * Assert to prevent misuse with other engines.
	 */
	GEM_BUG_ON(engine->class != RENDER_CLASS && engine->class != COPY_ENGINE_CLASS);
	GEM_BUG_ON(engine->instance != 0); /* Only BCS0 */

	/*
	 * MI_UPDATE_GTT can insert up to 511 PTE entries and there could be multiple
	 * bind requets at a time so get a bigger ring.
	 */
	return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_512K,
						  I915_GEM_HWS_GGTT_BIND_ADDR,
						  &kernel, "ggtt_bind_context");
}

```

- If `GEM_BUG_ON` or the engine class/instance macros are not available, you may need to adjust the assertion to match your codebase's conventions.
- If BCS0 is defined by a specific macro or constant (e.g., `BCS0`), use that instead of checking class/instance directly.
</issue_to_address>

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[sourcery-ai]

suggestion: The create_ggtt_bind_context function is only used for BCS0, but this is not enforced in the function itself.

Add an assertion or comment in create_ggtt_bind_context to clarify it should only be used with BCS0, preventing misuse with other engines.

Suggested implementation:

static struct intel_context *
create_ggtt_bind_context(struct intel_engine_cs *engine)
{
	static struct lock_class_key kernel;

	/*
	 * This function is intended to be used only with the BCS0 engine.
	 * Assert to prevent misuse with other engines.
	 */
	GEM_BUG_ON(engine->class != RENDER_CLASS && engine->class != COPY_ENGINE_CLASS);
	GEM_BUG_ON(engine->instance != 0); /* Only BCS0 */

	/*
	 * MI_UPDATE_GTT can insert up to 511 PTE entries and there could be multiple
	 * bind requets at a time so get a bigger ring.
	 */
	return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_512K,
						  I915_GEM_HWS_GGTT_BIND_ADDR,
						  &kernel, "ggtt_bind_context");
}

• If GEM_BUG_ON or the engine class/instance macros are not available, you may need to adjust the assertion to match your codebase's conventions.
• If BCS0 is defined by a specific macro or constant (e.g., BCS0), use that instead of checking class/instance directly.

[Copilot]

Pull Request Overview

This PR adds and refactors support for the Meteor Lake (Xe_LPG) platform across multiple DRM and GPU driver subsystems, replacing bespoke Meteor Lake checks with generic IP range/step macros, and introducing binder-based GGTT updates alongside cleanup of legacy MTL subplatform code.

• Consolidate Intel Meteor Lake PCI IDs and device info flags
• Refactor platform-specific workaround checks to use new IS_GFX_GT_IP_RANGE/STEP and IS_MEDIA_GT_IP_RANGE/STEP macros
• Introduce a dedicated GGTT binder context for PTE updates and extend PXP, GSC HECI, wakeref, MCHBAR, and reset WA handling

Reviewed Changes

Copilot reviewed 81 out of 81 changed files in this pull request and generated 1 comment.

Show a summary per file

File	Description
include/drm/i915_pciids.h	Consolidate MTL PCI ID macros
drivers/gpu/drm/i915/soc/intel_gmch.c	Factor out MCHBAR reg helper
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h	Add runtime resume prototype
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c	Refactor resume logic with wakeref
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h	Update GSCFW latency calculation
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c	Use new reply latency define
drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h	Adjust HECI packet size macro
drivers/gpu/drm/i915/intel_wakeref.c	Extend wakeref get/put logic
drivers/gpu/drm/i915/intel_device_info.h	Remove MTL subplatform defines
drivers/gpu/drm/i915/intel_device_info.c	Eliminate subplatform ID init
drivers/gpu/drm/i915/intel_clock_gating.c	Remove obsolete clock gating hooks
drivers/gpu/drm/i915/i915_scatterlist.h	Add iterator for daddr stepping
drivers/gpu/drm/i915/i915_perf_types.h	Remove unused override_gucrc field
drivers/gpu/drm/i915/i915_perf.c	Simplify OA stream logic
drivers/gpu/drm/i915/i915_pci.c	Add has_guc_tlb_invalidation flag
drivers/gpu/drm/i915/i915_gpu_error.c	Adjust ring fault read for media GT
drivers/gpu/drm/i915/i915_drv.h	Introduce DISPLAY_VER_FULL macro
drivers/gpu/drm/i915/i915_debugfs_params.c	Loop over GTs in notify_guc
drivers/gpu/drm/i915/i915_debugfs.c	Use IP range macro for cache levels
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c	Update GuC firmware definitions
drivers/gpu/drm/i915/gt/uc/intel_uc.c	Remove redundant HuC support check
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c	Replace MTL step WA with helper
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h	Remove unset/override GUCRC prototypes
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c	Remove gucrc override implementations
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h	Add TSC check WA bit
drivers/gpu/drm/i915/gt/uc/intel_guc.h	Define GUC_FIRMWARE_VER helper
drivers/gpu/drm/i915/gt/uc/intel_guc.c	Introduce GUC WA flags for MTL
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h	Define GSC_HECI_REPLY_LATENCY_MS
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c	Add delay handling in submit
drivers/gpu/drm/i915/gt/intel_workarounds.c	Remove MTL-specific workaround code
drivers/gpu/drm/i915/gt/intel_rps.c	Use IP version check for RPS caps
drivers/gpu/drm/i915/gt/intel_reset.h	Declare reset WA helper function
drivers/gpu/drm/i915/gt/intel_reset.c	Implement engine reset WA helper
drivers/gpu/drm/i915/gt/intel_rc6.c	Simplify power gating conditions
drivers/gpu/drm/i915/gt/intel_mocs.c	Use IP range macro in MOCS table
drivers/gpu/drm/i915/gt/intel_lrc.c	Add run-alone mode for protected contexts
drivers/gpu/drm/i915/gt/intel_gtt.h	Introduce bind iterator macro
drivers/gpu/drm/i915/gt/intel_gtt.c	Add binder context support for GGTT
drivers/gpu/drm/i915/gt/intel_gt_regs.h	Fix MTL CC mask bit range
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c	Remove incorrect missing_case macro
drivers/gpu/drm/i915/gt/intel_gt_pm.c	Add bind_context_set_ready calls
drivers/gpu/drm/i915/gt/intel_gt_mcr.h	Declare mcr lock sanitize function
drivers/gpu/drm/i915/gt/intel_gt_mcr.c	Implement lock sanitize for MTL
drivers/gpu/drm/i915/gt/intel_gt.h	Introduce IP range/step macros
drivers/gpu/drm/i915/gt/intel_gt.c	Handle media GT ring fault correctly
drivers/gpu/drm/i915/gt/intel_ggtt.c	Add GGTT bind page update path
drivers/gpu/drm/i915/gt/intel_execlists_submission.c	Use reset WA helper for reset prep
drivers/gpu/drm/i915/gt/intel_engine_types.h	Add bind_context field to engine
drivers/gpu/drm/i915/gt/intel_engine_regs.h	Introduce RUNALONE_MODE bit
drivers/gpu/drm/i915/gt/intel_engine_pm.c	Change idle message enable condition
drivers/gpu/drm/i915/gt/intel_engine_cs.c	Add ggtt_bind_context creation
drivers/gpu/drm/i915/gt/intel_engine.h	Define GGTT_BIND status page index
drivers/gpu/drm/i915/gt/gen8_engine_cs.c	Use IP range check for dummy PIPE_CONTROL
drivers/gpu/drm/i915/gem/i915_gem_stolen.c	Reserve DSM region for media workloads
drivers/gpu/drm/i915/gem/i915_gem_create.c	Restrict PAT extension to Xe_LPG
drivers/gpu/drm/i915/display/vlv_dsi.c	Consolidate DSI port ctrl regs
drivers/gpu/drm/i915/display/skl_universal_plane.c	Remove MTL plane workaround
drivers/gpu/drm/i915/display/intel_vdsc_regs.h	Refactor DSC PPS register macros

[Copilot]

i915_ggtt_require_binder() currently only returns true for MEDIA_VER_FULL == IP_VER(13,0), but GGTT binder support is needed for the Xe_LPG graphics GT (IP_VER 12,70+). Consider using IS_GFX_GT_IP_RANGE(gt, IP_VER(12,70), IP_VER(12,71)) or similar to detect the correct graphics GT platforms.

Suggested change

	return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
	return MEDIA_VER_FULL(i915) == IP_VER(13, 0) ||
	IS_GFX_GT_IP_RANGE(i915->gt, IP_VER(12, 70), IP_VER(12, 71));