1. https://www.cprover.org/ebmc/manual/tutorial/ 2. https://github.com/diffblue/hw-cbmc/blob/7fe06e486ef3a0d8b041e8416febf8f85e1c9a7b/regression/hw-cbmc/Counter2/main.v Sequential logic has to use non-blocking assignment: `<=` References: 1. > Avoid Assignment Mixing in Always Blocks > [Intel® Quartus® Prime Pro Edition synthesis does not allow mixed use of blocking and non-blocking assignments within ALWAYS blocks](https://www.intel.com/content/www/us/en/docs/programmable/683463/21-3/avoid-assignment-mixing-in-always-blocks.html) 2. >[Do not mix blocking and non-blocking assignments. Although Vivado synthesis synthesizes the design without error, mixing blocking and non-blocking assignments can cause errors during simulation.](https://docs.amd.com/r/en-US/ug901-vivado-synthesis/Blocking-and-Non-Blocking-Assignments)