KNOWNBUG test for module port constraints

regression/verilog/modules/ports9.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+ports9.sv
+--bound 1
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This gives the wrong answer.

regression/verilog/modules/ports9.sv

@@ -0,0 +1,15 @@
+module sub(input in, output logic data);
+
+  assign data = in;
+
+endmodule
+
+module main;
+  logic subout;
+
+  sub sub_inst(.data(subout));
+
+  // The value of the output needs to be able to change
+  cover property (##1 subout != $past(subout));
+
+endmodule