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Netlist engine: ignore various Verilog symbols #1361

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Merged
merged 1 commit into from
Oct 29, 2025
Merged

Netlist engine: ignore various Verilog symbols #1361

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3 changes: 3 additions & 0 deletions regression/verilog/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -7,3 +7,6 @@ test:

test-z3:
@$(TEST_PL) -e -p -c "../../../src/ebmc/ebmc --z3" -X broken-smt-backend

test-aig:
@$(TEST_PL) -e -p -c "../../../src/ebmc/ebmc --aig"
9 changes: 9 additions & 0 deletions regression/verilog/SVA/property_and1.aig.desc
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@@ -0,0 +1,9 @@
CORE
property_and1.sv
--aig --bound 5
^\[.*\] always \(main\.P1 and main\.P1\): PROVED up to bound 5$
^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
12 changes: 12 additions & 0 deletions src/trans-netlist/trans_to_netlist.cpp
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Expand Up @@ -211,6 +211,18 @@ void convert_trans_to_netlistt::map_vars(

if (symbol.is_property)
return; // ignore properties
else if(
symbol.type.id() == ID_verilog_sva_sequence ||
symbol.type.id() == ID_verilog_sva_property)
{
return; // ignore properties
}
else if(
symbol.type.id() == ID_natural || symbol.type.id() == ID_integer ||
symbol.type.id() == ID_verilog_genvar)
{
return; // ignore
}
else if(
symbol.type.id() == ID_module || symbol.type.id() == ID_module_instance ||
symbol.type.id() == ID_primitive_module_instance)
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