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SystemVerilog: add further $typename cases #1443

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Merged
tautschnig merged 1 commit into from
Nov 28, 2025
Merged

SystemVerilog: add further $typename cases #1443

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20 changes: 20 additions & 0 deletions src/verilog/typename.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -123,6 +123,26 @@ std::string verilog_typename(const typet &type)
else
return "bit signed[" + left(type) + ":" + right(type) + "]";
}
else if(type.id() == ID_verilog_byte)
{
return "byte";
}
else if(type.id() == ID_verilog_int)
{
return "int";
}
else if(type.id() == ID_verilog_integer)
{
return "integer";
}
else if(type.id() == ID_verilog_longint)
{
return "longint";
}
else if(type.id() == ID_verilog_shortint)
{
return "shortint";
}
else if(type.id() == ID_verilog_signedbv)
{
return "logic signed[" + left(type) + ":" + right(type) + "]";
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9 changes: 8 additions & 1 deletion unit/verilog/typename.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -14,10 +14,17 @@ SCENARIO("$typename(...)")
{
GIVEN("various Verilog types")
{
REQUIRE(verilog_typename(verilog_byte_typet{}) == "byte");
REQUIRE(verilog_typename(verilog_chandle_typet{}) == "chandle");
REQUIRE(verilog_typename(verilog_event_typet{}) == "event");
REQUIRE(verilog_typename(verilog_int_typet{}) == "int");
REQUIRE(verilog_typename(verilog_integer_typet{}) == "integer");
REQUIRE(verilog_typename(verilog_longint_typet{}) == "longint");
REQUIRE(verilog_typename(verilog_real_typet{}) == "real");
REQUIRE(verilog_typename(verilog_realtime_typet{}) == "realtime");
REQUIRE(verilog_typename(verilog_shortint_typet{}) == "shortint");
REQUIRE(verilog_typename(verilog_shortreal_typet{}) == "shortreal");
REQUIRE(
verilog_typename(verilog_signedbv_typet{10}) == "logic signed[9:0]");
REQUIRE(verilog_typename(verilog_shortreal_typet{}) == "shortreal");
}
}
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