Skip to content

Verilog: parameter assignments use base name #1453

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
tautschnig merged 1 commit into from
Dec 2, 2025
Merged

Verilog: parameter assignments use base name #1453

tautschnig merged 1 commit into from
Dec 2, 2025

Conversation

@kroening
Copy link
Collaborator

@kroening kroening commented Dec 2, 2025

Parameter assignments generated by the parser use a base name, not a fully qualified identifier.

@kroening
Verilog: parameter assignments use base name
0ef4d0a 
Parameter assignments generated by the parser use a base name, not a fully
qualified identifier.
@kroening kroening marked this pull request as ready for review December 2, 2025 16:10
@tautschnig tautschnig merged commit c6f7e41 into main Dec 2, 2025
11 checks passed
@tautschnig tautschnig deleted the verilog-param-base-name branch December 2, 2025 16:49
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

@tautschnig tautschnig tautschnig approved these changes

Assignees

No one assigned

Labels

cleanup Verilog

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

2 participants

@kroening @tautschnig