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@kroening kroening commented Dec 5, 2025

This fixes the check that errors when a module port is connected a second time.

This fixes the check that errors when a module port is connected a second time.
@kroening kroening force-pushed the named_port_connection1 branch from 9213c7b to 42bc94b Compare December 5, 2025 16:49
@kroening kroening changed the title Verilog: KNOWNBUG test for module port that is bound twice Verilog: error connecting the same port twice Dec 5, 2025
@kroening kroening marked this pull request as ready for review December 5, 2025 16:56
@tautschnig tautschnig merged commit b19ccd8 into main Dec 5, 2025
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@tautschnig tautschnig deleted the named_port_connection1 branch December 5, 2025 21:18
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2 participants