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SystemVerilog allows repeating the module identifier at after the endmodule keyword.

SystemVerilog allows repeating the module identifier at after the endmodule
keyword.
@kroening kroening marked this pull request as ready for review July 20, 2024 22:11
@tautschnig tautschnig merged commit cf0f84d into main Jul 22, 2024
@tautschnig tautschnig deleted the endmodule_identifier branch July 22, 2024 07:51
Romy15200 pushed a commit to Romy15200/nws that referenced this pull request Aug 19, 2025
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3 participants